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Update lab model to eleminate loops and add inputs

parent 0006b0de
package lab;
component Alex{
ports in Z loop,
out Z out1;
ports in Q input,
out Q out1;
implementation Math{
out1 = loop * loop;
out1 = input * input;
}
}
\ No newline at end of file
package lab;
component Combine{
ports in Z in1,
in Z in2,
in Z in3,
in Z in4,
out Z out1;
ports in Q in1,
in Q in2,
in Q in3,
in Q in4,
out Q out1;
implementation Math{
out1 = (in1 + in2 + in3 + in4) % 16;
out1 = cos(in1 + in2 + in3 + in4);
}
}
\ No newline at end of file
package lab;
component DinhAn{
ports in Z loop,
out Z out1;
ports in Q input,
out Q out1;
implementation Math{
static Z counter = 0;
counter = counter + 1;
out1 = (counter + 1) + loop;
out1 = input;
}
}
\ No newline at end of file
......@@ -4,20 +4,27 @@ conforms to de.monticore.lang.monticar.generator.roscpp.RosToEmamTagSchema;
tags LabTags {
//syntax: tag $port with RosConnection = {topic=($topicName,$topicType), msgField=$fieldOfTopicType};
tag system.alex.out1 with RosConnection = {topic=(/combine_in1,std_msgs/Int32), msgField=data};
tag system.dinhAn.out1 with RosConnection = {topic=(/combine_in2,std_msgs/Int32), msgField=data};
tag system.philipp.out1 with RosConnection = {topic=(/combine_in3,std_msgs/Int32), msgField=data};
tag system.michael.out1 with RosConnection = {topic=(/combine_in4,std_msgs/Int32), msgField=data};
tag system.rosIn[1] with RosConnection = {topic=(/in1,std_msgs/Float64), msgField=data};
tag system.rosIn[2] with RosConnection = {topic=(/in2,std_msgs/Float64), msgField=data};
tag system.rosIn[3] with RosConnection = {topic=(/in3,std_msgs/Float64), msgField=data};
tag system.rosIn[4] with RosConnection = {topic=(/in4,std_msgs/Float64), msgField=data};
tag system.combine.in1 with RosConnection = {topic=(/combine_in1,std_msgs/Int32), msgField=data};
tag system.combine.in2 with RosConnection ={topic=(/combine_in2,std_msgs/Int32), msgField=data};
tag system.combine.in3 with RosConnection = {topic=(/combine_in3,std_msgs/Int32), msgField=data};
tag system.combine.in4 with RosConnection = {topic=(/combine_in4,std_msgs/Int32), msgField=data};
tag system.alex.input with RosConnection = {topic=(/in1,std_msgs/Float64), msgField=data};
tag system.dinhAn.input with RosConnection = {topic=(/in2,std_msgs/Float64), msgField=data};
tag system.philipp.input with RosConnection = {topic=(/in3,std_msgs/Float64), msgField=data};
tag system.michael.input with RosConnection = {topic=(/in4,std_msgs/Float64), msgField=data};
tag system.alex.loop with RosConnection = {topic=(/combine_out,std_msgs/Int32), msgField=data};
tag system.dinhAn.loop with RosConnection = {topic=(/combine_out,std_msgs/Int32), msgField=data};
tag system.philipp.loop with RosConnection = {topic=(/combine_out,std_msgs/Int32), msgField=data};
tag system.michael.loop with RosConnection = {topic=(/combine_out,std_msgs/Int32), msgField=data};
tag system.alex.out1 with RosConnection = {topic=(/combine_in1,std_msgs/Float64), msgField=data};
tag system.dinhAn.out1 with RosConnection = {topic=(/combine_in2,std_msgs/Float64), msgField=data};
tag system.philipp.out1 with RosConnection = {topic=(/combine_in3,std_msgs/Float64), msgField=data};
tag system.michael.out1 with RosConnection = {topic=(/combine_in4,std_msgs/Float64), msgField=data};
tag system.combine.out1 with RosConnection = {topic=(/combine_out,std_msgs/Int32), msgField=data};
tag system.combine.in1 with RosConnection = {topic=(/combine_in1,std_msgs/Float64), msgField=data};
tag system.combine.in2 with RosConnection ={topic=(/combine_in2,std_msgs/Float64), msgField=data};
tag system.combine.in3 with RosConnection = {topic=(/combine_in3,std_msgs/Float64), msgField=data};
tag system.combine.in4 with RosConnection = {topic=(/combine_in4,std_msgs/Float64), msgField=data};
tag system.combine.out1 with RosConnection = {topic=(/combine_out,std_msgs/Float64), msgField=data};
tag system.rosOut with RosConnection = {topic=(/combine_out,std_msgs/Float64), msgField=data};
}
\ No newline at end of file
package lab;
component Michael{
ports in Z loop,
out Z out1;
ports in Q input,
out Q out1;
implementation Math{
out1 = loop + loop;
out1 = input + input;
}
}
package lab;
component Philipp{
ports in Z loop,
out Z out1;
ports in Q input,
out Q out1;
implementation Math{
out1 = loop + 1;
out1 = input + 1;
}
}
\ No newline at end of file
......@@ -2,19 +2,24 @@ package lab;
component System{
ports in Q rosIn[4],
out Q rosOut;
instance Alex alex;
instance DinhAn dinhAn;
instance Philipp philipp;
instance Michael michael;
instance Combine combine;
connect rosIn[1] -> alex.input;
connect rosIn[2] -> dinhAn.input;
connect rosIn[3] -> philipp.input;
connect rosIn[4] -> michael.input;
connect alex.out1 -> combine.in1;
connect dinhAn.out1 -> combine.in2;
connect philipp.out1 -> combine.in3;
connect michael.out1 -> combine.in4;
connect combine.out1 -> alex.loop;
connect combine.out1 -> dinhAn.loop;
connect combine.out1 -> philipp.loop;
connect combine.out1 -> michael.loop;
connect combine.out1 -> rosOut;
}
\ No newline at end of file
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