Commit 9bfbde33 authored by Ferdinand Keil's avatar Ferdinand Keil
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# ignore ModelSim generated files and directories (temp files and so on)
[_@]*
# ignore compilation output of ModelSim
*.mti
*.dat
*.dbs
*.psm
*.bak
*.cmp
*.jpg
*.html
*.bsf
# ignore simulation output of ModelSim
wlf*
*.wlf
*.vstf
*.ucdb
cov*/
transcript*
sc_dpiheader.h
vsim.dbg
# but include library "work"
!work/_info
module alu8 (input [7:0] left, right, input status_in, input [1:0] opcode, output reg status_out, output reg [7:0] result);
always @(left, right, status_in, opcode) begin
case (opcode)
0: {status_out, result} = left + right + status_in; // opcode 0: add with carry
1: {status_out, result} = left - right - status_in; // opcode 1: subtract with borrow
2: {status_out, result} = {1'b0, left & right}; // opcode 2: and
3: {status_out, result} = {1'b0, left | right}; // opcode 3: or
default: result = 8'bX; // default: undefined result
endcase
end
endmodule
`timescale 1ns/100ps
`define OP_ADD 0
`define OP_SUB 1
`define OP_AND 2
`define OP_OR 3
module alu8_tb ();
// define all input and outputs
reg [7:0] left, right;
reg status_in;
reg [1:0] opcode;
wire status_out;
wire [7:0] result;
// instantiate the module-under-test
alu8 alu_inst (
.left(left),
.right(right),
.status_in(status_in),
.opcode(opcode),
.status_out(status_out),
.result(result)
);
initial begin
// write the inputs and outputs to the log
$monitor("%g\t %g %g %b %g %b %g", $time, left, right, status_in, opcode, status_out, result);
// test the AND and OR operations with several inputs
left = 0;
right = 0;
status_in = 0;
opcode = OP_AND;
#1;
opcode = OP_OR;
#1;
left = 0;
right = 1;
opcode = OP_AND;
#1;
opcode = OP_OR;
#1;
left = 1;
right = 0;
opcode = OP_AND;
#1;
opcode = OP_OR;
#1;
left = 1;
right = 1;
opcode = OP_AND;
#1;
opcode = OP_OR;
#1;
left = 8'hAA;
right = 8'h55;
opcode = OP_AND;
#1;
opcode = OP_OR;
#1;
// add your tests here...
end
endmodule
; Copyright 1991-2014 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;
[Library]
std = $MODEL_TECH/../std
ieee = $MODEL_TECH/../ieee
vital2000 = $MODEL_TECH/../vital2000
;
; VITAL concerns:
;
; The library ieee contains (among other packages) the packages of the
; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use
; the physical library ieee (recommended), or use the physical library
; vital2000, but not both. The design can use logical library ieee and/or
; vital2000 as long as each of these maps to the same physical library, either
; ieee or vital2000.
;
; A design using the 1995 version of the VITAL packages, whether or not
; it also uses the 2000 version of the VITAL packages, must have logical library
; name ieee mapped to physical library vital1995. (A design cannot use library
; vital1995 directly because some packages in this library use logical name ieee
; when referring to the other packages in the library.) The design source
; should use logical name ieee when referring to any packages there except the
; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical
; name vital2000 (mapped to physical library vital2000) to refer to those
; packages.
; ieee = $MODEL_TECH/../vital1995
;
; For compatiblity with previous releases, logical library name vital2000 maps
; to library vital2000 (a different library than library ieee, containing the
; same packages).
; A design should not reference VITAL from both the ieee library and the
; vital2000 library because the vital packages are effectively different.
; A design that references both the ieee and vital2000 libraries must have
; both logical names ieee and vital2000 mapped to the same library, either of
; these:
; $MODEL_TECH/../ieee
; $MODEL_TECH/../vital2000
;
verilog = $MODEL_TECH/../verilog
std_developerskit = $MODEL_TECH/../std_developerskit
synopsys = $MODEL_TECH/../synopsys
modelsim_lib = $MODEL_TECH/../modelsim_lib
sv_std = $MODEL_TECH/../sv_std
mtiAvm = $MODEL_TECH/../avm
mtiOvm = $MODEL_TECH/../ovm-2.1.2
mtiUvm = $MODEL_TECH/../uvm-1.1d
mtiUPF = $MODEL_TECH/../upf_lib
mtiPA = $MODEL_TECH/../pa_lib
floatfixlib = $MODEL_TECH/../floatfixlib
mc2_lib = $MODEL_TECH/../mc2_lib
osvvm = $MODEL_TECH/../osvvm
;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
;mvc_lib = $MODEL_TECH/../mvc_lib
infact = $MODEL_TECH/../infact
vhdlopt_lib = $MODEL_TECH/../vhdlopt_lib
work = work
[DefineOptionset]
; Define optionset entries for the various compilers, vmake, and vsim.
; These option sets can be used with the "-optionset <optionsetname>" syntax.
; i.e.
; vlog -optionset COMPILEDEBUG top.sv
; vsim -optionset UVMDEBUG my_top
;
; Following are some useful examples.
; define a vsim optionset for uvm debugging
UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop
; define a vopt optionset for debugging
VOPTDEBUG = +acc -debugdb
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
; Value of 3 or 2008 for VHDL-2008
VHDL93 = 2002
; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off.
; ignoreStandardRealVector = 1
; Show source line containing error. Default is off.
; Show_source = 1
; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0
; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0
; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0
; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0
; Enable compiler statistics. Specify one or more arguments:
; [all,none,time,cmd,msg,perf,verbose,list]
; Add '-' to disable specific statistics. Default is [time,cmd,msg].
; Stats = time,cmd,msg
; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1
; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1
; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1
; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1
; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0
; Turn off PSL assertion warning messages. Default is to show warnings.
; Show_PslChecksWarnings = 0
; Enable parsing of embedded PSL assertions. Default is enabled.
; EmbeddedPsl = 0
; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1
; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1
; Treat as errors:
; case statement static warnings
; warnings caused by aggregates that are not locally static
; Overrides NoCaseStaticError, NoOthersStaticError settings.
; PedanticErrors = 1
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
; Turn on some limited synthesis rule compliance checking. Checks only:
; -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
; Turns on lint-style checking.
; Show_Lint = 1
; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1
; Perform default binding at compile time.
; Default is to do default binding at load time.
; BindAtCompile = 1;
; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1
; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1
; Set the prefix to be honored for synthesis/coverage pragma recognition.
; Default is "".
; AddPragmaPrefix = ""
; Ignore synthesis and coverage pragmas with this prefix.
; Default is "".
; IgnorePragmaPrefix = ""
; Turn on code coverage in VHDL design units. Default is off.
; Coverage = sbceft
; Turn off code coverage in VHDL subprograms. Default is on.
; CoverSub = 0
; Automatically exclude VHDL case statement OTHERS choice branches.
; This includes OTHERS choices in selected signal assigment statements.
; Default is to not exclude.
; CoverExcludeDefault = 1
; Control compiler and VOPT optimizations that are allowed when
; code coverage is on. Refer to the comment for this in the [vlog] area.
; CoverOpt = 3
; Turn on or off clkOpt optimization for code coverage. Default is on.
; CoverClkOpt = 1
; Turn on or off clkOpt optimization builtins for code coverage. Default is on.
; CoverClkOptBuiltins = 0
; Inform code coverage optimizations to respect VHDL 'H' and 'L'
; values on signals in conditions and expressions, and to not automatically
; convert them to '1' and '0'. Default is to not convert.
; CoverRespectHandL = 0
; Increase or decrease the maximum number of rows allowed in a UDP table
; implementing a VHDL condition coverage or expression coverage expression.
; More rows leads to a longer compile time, but more expressions covered.
; CoverMaxUDPRows = 192
; Increase or decrease the maximum number of input patterns that are present
; in FEC table. This leads to a longer compile time with more expressions
; covered with FEC metric.
; CoverMaxFECRows = 192
; Increase or decrease the limit on the size of expressions and conditions
; considered for expression and condition coverages. Higher FecUdpEffort leads
; to higher compile, optimize and simulation time, but more expressions and
; conditions are considered for coverage in the design. FecUdpEffort can
; be set to a number ranging from 1 (low) to 3 (high), defined as:
; 1 - (low) Only small expressions and conditions considered for coverage.
; 2 - (medium) Bigger expressions and conditions considered for coverage.
; 3 - (high) Very large expressions and conditions considered for coverage.
; The default setting is 1 (low).
; FecUdpEffort = 1
; Enable or disable Focused Expression Coverage analysis for conditions and
; expressions. Focused Expression Coverage data is provided by default when
; expression and/or condition coverage is active.
; CoverFEC = 0
; Enable or disable UDP Coverage analysis for conditions and expressions.
; UDP Coverage data is disabled by default when expression and/or condition
; coverage is active.
; CoverUDP = 1
; Enable or disable Rapid Expression Coverage mode for conditions and expressions.
; Disabling this would convert non-masking conditions in FEC tables to matching
; input patterns.
; CoverREC = 1
; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions
; for expression/condition coverage.
; NOTE: Enabling this may have a negative impact on simulation performance.
; CoverExpandReductionPrefix = 0
; Enable or disable short circuit evaluation of conditions and expressions when
; condition or expression coverage is active. Short circuit evaluation is enabled
; by default.
; CoverShortCircuit = 0
; Enable code coverage reporting of code that has been optimized away.
; The default is not to report.
; CoverReportCancelled = 1
; Enable deglitching of code coverage in combinatorial, non-clocked, processes.
; Default is no deglitching.
; CoverDeglitchOn = 1
; Control the code coverage deglitching period. A period of 0, eliminates delta
; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a
; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
; CoverDeglitchPeriod = 0
; Use this directory for compiler temporary files instead of "work/_temp"
; CompilerTempDir = /tmp
; Set this to cause the compilers to force data to be committed to disk
; when the files are closed.
; SyncCompilerFiles = 1
; Add VHDL-AMS declarations to package STANDARD
; Default is not to add
; AmsStandard = 1
; Range and length checking will be performed on array indices and discrete
; ranges, and when violations are found within subprograms, errors will be
; reported. Default is to issue warnings for violations, because subprograms
; may not be invoked.
; NoDeferSubpgmCheck = 0
; Turn ON detection of FSMs having single bit current state variable.
; FsmSingle = 1
; Turn off reset state transitions in FSM.
; FsmResetTrans = 0
; Turn ON detection of FSM Implicit Transitions.
; FsmImplicitTrans = 1
; Controls whether or not to show immediate assertions with constant expressions
; in GUI/report/UCDB etc. By default, immediate assertions with constant
; expressions are shown in GUI/report/UCDB etc. This does not affect
; evaluation of immediate assertions.
; ShowConstantImmediateAsserts = 0
; Controls how VHDL basic identifiers are stored with the design unit.
; Does not make the language case-sensitive, affects only how declarations
; declared with basic identifiers have their names stored and printed
; (in the GUI, examine, etc.).
; Default is to preserve the case as originally depicted in the VHDL source.
; Value of 0 indicates to change all basic identifiers to lower case.
; PreserveCase = 0
; For Configuration Declarations, controls the effect that USE clauses have
; on visibility inside the configuration items being configured. If 1
; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance,
; extend the visibility of objects made visible through USE clauses into nested
; component configurations.
; OldVHDLConfigurationVisibility = 0
; Allows VHDL configuration declarations to be in a different library from
; the corresponding configured entity. Default is to not allow this for
; stricter LRM-compliance.
; SeparateConfigLibrary = 1;
; Determine how mode OUT subprogram parameters of type array and record are treated.
; If 0 (the default), then only VHDL 2008 will do this initialization.
; If 1, always initialize the mode OUT parameter to its default value.
; If 2, do not initialize the mode OUT out parameter.
; Note that prior to release 10.1, all language versions did not initialize mode
; OUT array and record type parameters, unless overridden here via this mechanism.
; In release 10.1 and later, only files compiled with VHDL 2008 will cause this
; initialization, unless overridden here.
; InitOutCompositeParam = 0
; Generate symbols debugging database in only some special cases to save on
; the number of files in the library. For other design-units, this database is
; generated on-demand in vsim.
; Default is to to generate debugging database for all design-units.
; SmartDbgSym = 1
[vlog]
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
; Turn on `protect compiler directive processing.
; Default is to ignore `protect directives.
; Protect = 1
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1
; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
; Turns on lint-style checking.
; Show_Lint = 1
; Show source line containing error. Default is off.
; Show_source = 1
; Turn on bad option warning. Default is off.
; Show_BadOptionWarning = 1
; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
; vlog95compat = 1
; Turn off PSL warning messages. Default is to show warnings.
; Show_PslChecksWarnings = 0
; Enable parsing of embedded PSL assertions. Default is enabled.
; EmbeddedPsl = 0
; Enable compiler statistics. Specify one or more arguments:
; [all,none,time,cmd,msg,perf,verbose,list]
; Add '-' to disable specific statistics. Default is [time,cmd,msg].
; Stats = time,cmd,msg
; Set the threshold for automatically identifying sparse Verilog memories.
; A memory with depth equal to or more than the sparse memory threshold gets
; marked as sparse automatically, unless specified otherwise in source code
; or by +nosparse commandline option of vlog or vopt.
; The default is 1M. (i.e. memories with depth equal
; to or greater than 1M are marked as sparse)
; SparseMemThreshold = 1048576
; Set the prefix to be honored for synthesis and coverage pragma recognition.
; Default is "".
; AddPragmaPrefix = ""
; Ignore synthesis and coverage pragmas with this prefix.
; Default is "".
; IgnorePragmaPrefix = ""
; Set the option to treat all files specified in a vlog invocation as a
; single compilation unit. The default value is set to 0 which will treat
; each file as a separate compilation unit as specified in the P1800 draft standard.
; MultiFileCompilationUnit = 1
; Turn on code coverage in Verilog design units. Default is off.
; Coverage = sbceft
; Automatically exclude Verilog case statement default branches.
; Default is to not automatically exclude defaults.
; CoverExcludeDefault = 1
; Increase or decrease the maximum number of rows allowed in a UDP table
; implementing a VHDL condition coverage or expression coverage expression.
; More rows leads to a longer compile time, but more expressions covered.
; CoverMaxUDPRows = 192
; Increase or decrease the maximum number of input patterns that are present
; in FEC table. This leads to a longer compile time with more expressions
; covered with FEC metric.
; CoverMaxFECRows = 192
; Increase or decrease the limit on the size of expressions and conditions
; considered for expression and condition coverages. Higher FecUdpEffort leads
; to higher compile, optimize and simulation time, but more expressions and
; conditions are considered for coverage in the design. FecUdpEffort can
; be set to a number ranging from 1 (low) to 3 (high), defined as:
; 1 - (low) Only small expressions and conditions considered for coverage.
; 2 - (medium) Bigger expressions and conditions considered for coverage.
; 3 - (high) Very large expressions and conditions considered for coverage.
; The default setting is 1 (low).
; FecUdpEffort = 1
; Enable or disable Focused Expression Coverage analysis for conditions and
; expressions. Focused Expression Coverage data is provided by default when
; expression and/or condition coverage is active.
; CoverFEC = 0
; Enable or disable UDP Coverage analysis for conditions and expressions.
; UDP Coverage data is disabled by default when expression and/or condition
; coverage is active.
; CoverUDP = 1
; Enable or disable Rapid Expression Coverage mode for conditions and expressions.
; Disabling this would convert non-masking conditions in FEC tables to matching
; input patterns.
; CoverREC = 1
; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions
; for expression/condition coverage.
; NOTE: Enabling this may have a negative impact on simulation performance.
; CoverExpandReductionPrefix = 0
; Enable or disable short circuit evaluation of conditions and expressions when
; condition or expression coverage is active. Short circuit evaluation is enabled
; by default.
; CoverShortCircuit = 0
; Enable deglitching of code coverage in combinatorial, non-clocked, processes.
; Default is no deglitching.
; CoverDeglitchOn = 1
; Control the code coverage deglitching period. A period of 0, eliminates delta
; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a
; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
; CoverDeglitchPeriod = 0
; Turn on code coverage in VLOG `celldefine modules, modules containing
; specify blocks, and modules included using vlog -v and -y. Default is off.
; CoverCells = 1
; Enable code coverage reporting of code that has been optimized away.
; The default is not to report.
; CoverReportCancelled = 1
; Control compiler and VOPT optimizations that are allowed when
; code coverage is on. This is a number from 0 to 5, with the following
; meanings (the default is 3):
; 5 -- All allowable optimizations are on.
; 4 -- Turn off removing unreferenced code.
; 3 -- Turn off process, always block and if statement merging.
; 2 -- Turn off expression optimization, converting primitives
; to continuous assignments, VHDL subprogram inlining.
; and VHDL clkOpt (converting FF's to builtins).
; 1 -- Turn off continuous assignment optimizations and clock suppression.
; 0 -- Turn off Verilog module inlining and VHDL arch inlining.
; HOWEVER, if fsm coverage is turned on, optimizations will be forced to
; level 3, with also turning off converting primitives to continuous assigns.
; CoverOpt = 3
; Specify the override for the default value of "cross_num_print_missing"
; option for the Cross in Covergroups. If not specified then LRM default
; value of 0 (zero) is used. This is a compile time option.
; SVCrossNumPrintMissingDefault = 0
; Setting following to 1 would cause creation of variables which
; would represent the value of Coverpoint expressions. This is used
; in conjunction with "SVCoverpointExprVariablePrefix" option
; in the modelsim.ini
; EnableSVCoverpointExprVariable = 0
; Specify the override for the prefix used in forming the variable names
; which represent the Coverpoint expressions. This is used in conjunction with
; "EnableSVCoverpointExprVariable" option of the modelsim.ini
; The default prefix is "expr".
; The variable name is
; variable name => <prefix>_<coverpoint name>
; SVCoverpointExprVariablePrefix = expr
; Override for the default value of the SystemVerilog covergroup,
; coverpoint, and cross option.goal (defined to be 100 in the LRM).
; NOTE: It does not override specific assignments in SystemVerilog
; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
; in the [vsim] section can override this value.
; SVCovergroupGoalDefault = 100
; Override for the default value of the SystemVerilog covergroup,
; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
; NOTE: It does not override specific assignments in SystemVerilog
; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
; in the [vsim] section can override this value.
; SVCovergroupTypeGoalDefault = 100
; Specify the override for the default value of "strobe" option for the
; Covergroup Type. This is a compile time option which forces "strobe" to
; a user specified default value and supersedes SystemVerilog specified
; default value of '0'(zero). NOTE: This can be overriden by a runtime
; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.