Commit 9bfbde33 authored by Ferdinand Keil's avatar Ferdinand Keil
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# ignore ModelSim generated files and directories (temp files and so on)
[_@]*
# ignore compilation output of ModelSim
*.mti
*.dat
*.dbs
*.psm
*.bak
*.cmp
*.jpg
*.html
*.bsf
# ignore simulation output of ModelSim
wlf*
*.wlf
*.vstf
*.ucdb
cov*/
transcript*
sc_dpiheader.h
vsim.dbg
# but include library "work"
!work/_info
module alu8 (input [7:0] left, right, input status_in, input [1:0] opcode, output reg status_out, output reg [7:0] result);
always @(left, right, status_in, opcode) begin
case (opcode)
0: {status_out, result} = left + right + status_in; // opcode 0: add with carry
1: {status_out, result} = left - right - status_in; // opcode 1: subtract with borrow
2: {status_out, result} = {1'b0, left & right}; // opcode 2: and
3: {status_out, result} = {1'b0, left | right}; // opcode 3: or
default: result = 8'bX; // default: undefined result
endcase
end
endmodule
`timescale 1ns/100ps
`define OP_ADD 0
`define OP_SUB 1
`define OP_AND 2
`define OP_OR 3
module alu8_tb ();
// define all input and outputs
reg [7:0] left, right;
reg status_in;
reg [1:0] opcode;
wire status_out;
wire [7:0] result;
// instantiate the module-under-test
alu8 alu_inst (
.left(left),
.right(right),
.status_in(status_in),
.opcode(opcode),
.status_out(status_out),
.result(result)
);
initial begin
// write the inputs and outputs to the log
$monitor("%g\t %g %g %b %g %b %g", $time, left, right, status_in, opcode, status_out, result);
// test the AND and OR operations with several inputs
left = 0;
right = 0;
status_in = 0;
opcode = OP_AND;
#1;
opcode = OP_OR;
#1;
left = 0;
right = 1;
opcode = OP_AND;
#1;
opcode = OP_OR;
#1;
left = 1;
right = 0;
opcode = OP_AND;
#1;
opcode = OP_OR;
#1;
left = 1;
right = 1;
opcode = OP_AND;
#1;
opcode = OP_OR;
#1;
left = 8'hAA;
right = 8'h55;
opcode = OP_AND;
#1;
opcode = OP_OR;
#1;
// add your tests here...
end
endmodule
This diff is collapsed.
#!/bin/csh -f
# This loads the module for ModelSim and then starts it.
# Running in a subshell suppresses messages like [PID] or
# Done. And all output is redirected to /dev/null. The
# option novopt disables optimisation, which is necessary
# for the simulation to work.
(module load modelsim/10.3d; vsim -novopt &) >& /dev/null
m255
K4
z2
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
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