Commit ff07bc39 authored by Steffen Vogel's avatar Steffen Vogel 🎅🏼
Browse files

refactor: no namespace scoeps in source files

parent 1eb8f523
......@@ -39,8 +39,8 @@
#include "kernels.hpp"
namespace villas {
namespace gpu {
using namespace villas::gpu;
static GpuFactory gpuFactory;
......@@ -523,6 +523,3 @@ GpuFactory::make()
return gpuList;
}
} // namespace villas
} // namespace gpu
......@@ -24,24 +24,24 @@
#include <memory>
#include <utility>
#include <villas/exceptions.hpp>
#include <villas/memory.hpp>
#include <villas/kernel/pci.h>
#include <villas/kernel/pci.hpp>
#include <villas/kernel/vfio.hpp>
#include <villas/fpga/core.hpp>
#include <villas/fpga/card.hpp>
namespace villas {
namespace fpga {
using namespace villas::fpga;
// instantiate factory to register
static PCIeCardFactory PCIeCardFactory;
CardList
PCIeCardFactory::make(json_t *json, struct pci* pci, std::shared_ptr<VfioContainer> vc)
PCIeCard::List
PCIeCardFactory::make(json_t *json, kernel::pci::DeviceList *pci, std::shared_ptr<kernel::vfio::Container> vc)
{
CardList cards;
PCIeCard::List cards;
auto logger = getStaticLogger();
const char *card_name;
......@@ -74,7 +74,7 @@ PCIeCardFactory::make(json_t *json, struct pci* pci, std::shared_ptr<VfioContain
card->pci = pci;
card->vfioContainer = std::move(vc);
card->affinity = affinity;
card->do_reset = do_reset != 0;
card->doReset = do_reset != 0;
const char* error;
......@@ -86,22 +86,20 @@ PCIeCardFactory::make(json_t *json, struct pci* pci, std::shared_ptr<VfioContain
logger->warn("Failed to parse PCI ID: {}", error);
}
if (not card->init()) {
logger->warn("Cannot start FPGA card {}", card_name);
continue;
}
if (not json_is_object(json_ips))
throw ConfigError(json_ips, "node-config-fpga-ips", "FPGA IP core list must be an object!");
card->ips = ip::CoreFactory::make(card.get(), json_ips);
if (card->ips.empty()) {
logger->error("Cannot initialize IPs of FPGA card {}", card_name);
continue;
}
if (card->ips.empty())
throw ConfigError(json_ips, "node-config-fpga-ips", "Cannot initialize IPs of FPGA card {}", card_name);
if (not card->check()) {
logger->warn("Checking of FPGA card {} failed", card_name);
continue;
}
if (not card->check())
throw RuntimeError("Checking of FPGA card {} failed", card_name);
cards.push_back(std::move(card));
}
......@@ -231,8 +229,8 @@ PCIeCard::init()
}
/* Attach PCIe card to VFIO container */
VfioDevice& device = vfioContainer->attachDevice(pdev);
this->vfioDevice = &device;
kernel::vfio::Device &device = vfioContainer->attachDevice(pdev);
this->kernel::vfio::Device = &device;
/* Enable memory access and PCI bus mastering for DMA */
if (not device.pciEnable()) {
......@@ -241,9 +239,9 @@ PCIeCard::init()
}
/* Reset system? */
if (do_reset) {
if (doReset) {
/* Reset / detect PCI device */
if (not vfioDevice->pciHotReset()) {
if (not kernel::vfio::Device->pciHotReset()) {
logger->error("Failed to reset PCI device");
return false;
}
......@@ -256,6 +254,3 @@ PCIeCard::init()
return true;
}
} // namespace fpga
} // namespace villas
......@@ -37,9 +37,7 @@
#include <villas/fpga/ips/switch.hpp>
namespace villas {
namespace fpga {
namespace ip {
using namespace villas::fpga::ip;
// Special IPs that have to be initialized first. Will be initialized in the
// same order as they appear in this list, i.e. first here will be initialized
......@@ -364,8 +362,3 @@ Core::getInterruptController(const std::string &interruptName) const
return nullptr;
}
}
} // namespace ip
} // namespace fpga
} // namespace villas
......@@ -66,9 +66,7 @@
#define AURORA_AXIS_CR_SEQ_ECHO (1 << 4)
namespace villas {
namespace fpga {
namespace ip {
using namespace villas::fpga::ip;
static AuroraFactory auroraFactoryInstance;
......@@ -118,7 +116,3 @@ void Aurora::resetFrameCounters()
writeMemory<uint32_t>(registerMemory, AURORA_AXIS_CR_OFFSET, cr);
}
} // namespace ip
} // namespace fpga
} // namespace villas
......@@ -22,9 +22,7 @@
#include <villas/fpga/ips/bram.hpp>
namespace villas {
namespace fpga {
namespace ip {
using namespace villas::fpga::ip;
static BramFactory factory;
......@@ -49,6 +47,3 @@ bool Bram::init()
return true;
}
} // namespace ip
} // namespace fpga
} // namespace villas
......@@ -35,9 +35,7 @@
#define FPGA_DMA_BOUNDARY 0x1000
namespace villas {
namespace fpga {
namespace ip {
using namespace villas::fpga::ip;
// instantiate factory to make available to plugin infrastructure
static DmaFactory factory;
......@@ -401,7 +399,3 @@ Dma::dump()
logger->info("S2MM_LENGTH: {:x}", XAxiDma_ReadReg(xDma.RegBase, XAXIDMA_RX_OFFSET + XAXIDMA_BUFFLEN_OFFSET));
}
} // namespace ip
} // namespace fpga
} // namespace villas
......@@ -32,9 +32,7 @@
#include <villas/fpga/ips/intc.hpp>
namespace villas {
namespace fpga {
namespace ip {
using namespace villas::fpga::ip;
// instantiate factory to make available to plugin infrastructure
static FifoFactory factory;
......@@ -113,6 +111,3 @@ size_t Fifo::read(void *buf, size_t len)
return nextlen;
}
} // namespace ip
} // namespace fpga
} // namespace villas
......@@ -31,9 +31,7 @@
#include <villas/fpga/card.hpp>
#include <villas/fpga/ips/gpio.hpp>
namespace villas {
namespace fpga {
namespace ip {
using namespace villas::fpga::ip;
// instantiate factory to make available to plugin infrastructure
......@@ -47,6 +45,3 @@ GeneralPurposeIO::init()
return true;
}
} // namespace ip
} // namespace fpga
} // namespace villas
......@@ -31,10 +31,7 @@
#include <villas/fpga/card.hpp>
#include <villas/fpga/ips/intc.hpp>
namespace villas {
namespace fpga {
namespace ip {
using namespace villas::fpga::ip;
// instantiate factory to make available to plugin infrastructure
static InterruptControllerFactory factory;
......@@ -171,6 +168,3 @@ InterruptController::waitForInterrupt(int irq)
}
}
} // namespace ip
} // namespace fpga
} // namespace villas
......@@ -29,9 +29,7 @@
#include <villas/fpga/ips/pcie.hpp>
namespace villas {
namespace fpga {
namespace ip {
using namespace villas::fpga::ip;
static AxiPciExpressBridgeFactory factory;
......@@ -170,7 +168,3 @@ AxiPciExpressBridgeFactory::configureJson(Core &ip, json_t* json_ip)
return true;
}
} // namespace ip
} // namespace fpga
} // namespace villas
......@@ -53,9 +53,7 @@
/* Control register bits */
#define RTDS_AXIS_CR_DISABLE_LINK 0 /**< Disable SFP TX when set */
namespace villas {
namespace fpga {
namespace ip {
using namespace villas::fpga::ip;
static RtdsFactory rtdsFactoryInstance;
......@@ -92,6 +90,3 @@ double Rtds::getDt()
return (dt == 0xFFFF) ? 0.0 : (double) dt / RTDS_HZ;
}
} // namespace ip
} // namespace fpga
} // namespace villas
......@@ -5,9 +5,7 @@
#include <villas/memory_manager.hpp>
#include <villas/fpga/ips/gpu2rtds.hpp>
namespace villas {
namespace fpga {
namespace ip {
using namespace villas::fpga::ip;
static Gpu2RtdsFactory factory;
......@@ -131,6 +129,3 @@ Gpu2Rtds::getMaxFrameSize()
// logger->info(" Seq. number: {}", doorbell.seq_nr);
//}
} // namespace ip
} // namespace fpga
} // namespace villas
......@@ -5,10 +5,7 @@
#include <villas/memory_manager.hpp>
#include <villas/fpga/ips/rtds2gpu.hpp>
namespace villas {
namespace fpga {
namespace ip {
using namespace villas::fpga::ip;
static Rtds2GpuFactory factory;
bool Rtds2Gpu::init()
......@@ -28,8 +25,6 @@ bool Rtds2Gpu::init()
return true;
}
void Rtds2Gpu::dump(spdlog::level::level_enum logLevel)
{
const auto baseaddr = XRtds2gpu_Get_baseaddr(&xInstance);
......@@ -116,6 +111,3 @@ Rtds2Gpu::dumpDoorbell(uint32_t doorbellRegister) const
logger->info(" Seq. number: {}", doorbell.seq_nr);
}
} // namespace ip
} // namespace fpga
} // namespace villas
......@@ -30,9 +30,7 @@
#include <villas/fpga/ips/timer.hpp>
#include <villas/fpga/ips/intc.hpp>
namespace villas {
namespace fpga {
namespace ip {
using namespace villas::fpga::ip;
// instantiate factory to make available to plugin infrastructure
......@@ -80,8 +78,3 @@ uint32_t Timer::remaining()
{
return XTmrCtr_GetValue(&xTmr, 0);
}
} // namespace ip
} // namespace fpga
} // namespace villas
......@@ -25,7 +25,7 @@
#include <villas/memory.hpp>
namespace villas {
using namespace villas;
bool
HostRam::free(void* addr, size_t length)
......@@ -42,5 +42,3 @@ HostRam::allocate(size_t length, int flags)
return mmap(nullptr, length, mmap_protection, mmap_flags, 0, 0);
}
} // namespace villas
......@@ -30,10 +30,7 @@
#include <villas/fpga/node.hpp>
#include <villas/fpga/ips/switch.hpp>
namespace villas {
namespace fpga {
namespace ip {
using namespace villas::fpga::ip;
StreamGraph
Node::streamGraph;
......@@ -214,7 +211,3 @@ Node::connectLoopback()
return connect(*portMaster, *portSlave);
}
} // namespace ip
} // namespace fpga
} // namespace villas
......@@ -25,8 +25,7 @@
#include <villas/fpga/vlnv.hpp>
namespace villas {
namespace fpga {
using namespace villas::fpga;
bool
Vlnv::operator==(const Vlnv &other) const
......@@ -74,5 +73,3 @@ Vlnv::toString() const
return string;
}
} // namespace fpga
} // namespace villas
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