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ACS
Public
VILLASframework
VILLASfpga
VILLASfpga
Commits
f11a7a3f
Commit
f11a7a3f
authored
Jun 04, 2018
by
Daniel Krebs
Browse files
ip-node: move stream graph to IpNode and add easy-to-use connect interface
parent
28891cd2
Changes
3
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include/villas/fpga/ip_node.hpp
View file @
f11a7a3f
...
...
@@ -86,11 +86,6 @@ public:
};
extern
StreamGraph
streamGraph
;
// TODO: reflect on interface that an IpNode exposes and how to design it to
// blend in with VILLASnode software nodes
class
IpNode
:
public
IpCore
{
public:
...
...
@@ -102,7 +97,6 @@ public:
};
bool
connect
(
const
StreamVertex
&
from
,
const
StreamVertex
&
to
);
bool
disconnect
(
std
::
string
portName
);
const
StreamVertex
&
getMasterPort
(
const
std
::
string
&
name
)
const
...
...
@@ -112,6 +106,20 @@ public:
getSlavePort
(
const
std
::
string
&
name
)
const
{
return
*
portsSlave
.
at
(
name
);
}
// easy-usage assuming that the slave IP to connect to only has one slave
// port and implements the getDefaultSlavePort() function
bool
connect
(
const
IpNode
&
slaveNode
)
{
return
this
->
connect
(
this
->
getDefaultMasterPort
(),
slaveNode
.
getDefaultSlavePort
());
}
// used by easy-usage connect, will throw if not implemented by derived node
virtual
const
StreamVertex
&
getDefaultSlavePort
()
const
;
// used by easy-usage connect, will throw if not implemented by derived node
virtual
const
StreamVertex
&
getDefaultMasterPort
()
const
;
bool
loopbackPossible
()
const
;
bool
connectLoopback
();
...
...
@@ -126,6 +134,8 @@ private:
protected:
std
::
map
<
std
::
string
,
std
::
shared_ptr
<
StreamVertex
>>
portsMaster
;
std
::
map
<
std
::
string
,
std
::
shared_ptr
<
StreamVertex
>>
portsSlave
;
static
StreamGraph
streamGraph
;
};
class
IpNodeFactory
:
public
IpCoreFactory
{
...
...
include/villas/fpga/ips/dma.hpp
View file @
f11a7a3f
...
...
@@ -60,6 +60,14 @@ public:
hasScatterGather
()
const
{
return
hasSG
;
}
const
StreamVertex
&
getDefaultSlavePort
()
const
{
return
getSlavePort
(
s2mmPort
);
}
const
StreamVertex
&
getDefaultMasterPort
()
const
{
return
getMasterPort
(
mm2sPort
);
}
private:
bool
writeSG
(
const
void
*
buf
,
size_t
len
);
bool
readSG
(
void
*
buf
,
size_t
len
);
...
...
lib/ip_node.cpp
View file @
f11a7a3f
...
...
@@ -13,7 +13,8 @@ namespace fpga {
namespace
ip
{
StreamGraph
streamGraph
;
StreamGraph
IpNode
::
streamGraph
;
bool
IpNodeFactory
::
configureJson
(
IpCore
&
ip
,
json_t
*
json_ip
)
...
...
@@ -55,20 +56,20 @@ IpNodeFactory::configureJson(IpCore& ip, json_t* json_ip)
const
bool
isMaster
=
(
role
==
"master"
or
role
==
"initiator"
);
auto
thisVertex
=
streamGraph
.
getOrCreateStreamVertex
(
auto
thisVertex
=
IpNode
::
streamGraph
.
getOrCreateStreamVertex
(
ip
.
getInstanceName
(),
name_raw
,
isMaster
);
auto
connectedVertex
=
streamGraph
.
getOrCreateStreamVertex
(
auto
connectedVertex
=
IpNode
::
streamGraph
.
getOrCreateStreamVertex
(
tokens
[
0
],
tokens
[
1
],
not
isMaster
);
if
(
isMaster
)
{
streamGraph
.
addDefaultEdge
(
thisVertex
->
getIdentifier
(),
connectedVertex
->
getIdentifier
());
IpNode
::
streamGraph
.
addDefaultEdge
(
thisVertex
->
getIdentifier
(),
connectedVertex
->
getIdentifier
());
ipNode
.
portsMaster
[
name_raw
]
=
thisVertex
;
}
else
/* slave */
{
ipNode
.
portsSlave
[
name_raw
]
=
thisVertex
;
...
...
@@ -143,6 +144,20 @@ bool IpNode::connect(const StreamVertex& from, const StreamVertex& to)
return
nextHopNodeIp
->
connect
(
*
nextHopNode
,
to
);
}
const
StreamVertex
&
IpNode
::
getDefaultSlavePort
()
const
{
logger
->
error
(
"No default slave port available"
);
throw
std
::
exception
();
}
const
StreamVertex
&
IpNode
::
getDefaultMasterPort
()
const
{
logger
->
error
(
"No default master port available"
);
throw
std
::
exception
();
}
bool
IpNode
::
loopbackPossible
()
const
{
...
...
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