Commit c8914573 authored by Steffen Vogel's avatar Steffen Vogel 🎅🏼
Browse files

fix code-style

parent e73d84f1
Pipeline #319855 failed with stages
in 57 seconds
......@@ -121,8 +121,7 @@ bool Gpu::registerIoMemory(const MemoryBlock &mem)
return true;
else
logger->warn("There's already a mapping, but too small");
}
catch(const std::out_of_range&) {
} catch (const std::out_of_range&) {
// not yet reachable, that's okay, proceed
}
......@@ -154,7 +153,7 @@ bool Gpu::registerIoMemory(const MemoryBlock &mem)
mappedBaseAddrSpaceId);
baseAddrOnPci = translationPci.getLocalAddr(0);
sizeOnPci = translationPci.getSize();
} catch(const std::out_of_range&) {
} catch (const std::out_of_range&) {
logger->error("Memory is not reachable via PCIe bus");
return false;
}
......@@ -324,7 +323,7 @@ Gpu::makeAccessibleFromPCIeOrHostRam(const MemoryBlock &mem)
try {
auto path = mm.findPath(mm.getPciAddressSpace(), mem.getAddrSpaceId());
isIoMemory = true;
} catch(const std::out_of_range&) {
} catch (const std::out_of_range&) {
// not reachable via PCI -> not IO memory
}
......
......@@ -178,7 +178,7 @@ CoreFactory::make(PCIeCard* card, json_t *json_ips)
int num;
try {
num = std::stoi(tokens[1]);
} catch(const std::invalid_argument&) {
} catch (const std::invalid_argument&) {
logger->warn("IRQ number is not an integer: '{}'", irqEntry);
continue;
}
......@@ -357,7 +357,7 @@ Core::getInterruptController(const std::string &interruptName) const
try {
const IrqPort irq = irqs.at(interruptName);
return irq.irqController;
} catch(const std::out_of_range&) {
} catch (const std::out_of_range&) {
return nullptr;
}
}
......@@ -381,7 +381,7 @@ Dma::isMemoryBlockAccesible(const MemoryBlock &mem, const std::string &interface
try {
mm.findPath(getMasterAddrSpaceByInterface(interface), mem.getAddrSpaceId());
} catch(const std::out_of_range&) {
} catch (const std::out_of_range&) {
// not (yet) accessible
return false;
}
......
......@@ -47,7 +47,7 @@ bool Fifo::init()
// if this throws an exception, then there's no AXI4 data interface
fifo_cfg.Axi4BaseAddress = getBaseAddr(axi4Memory);
fifo_cfg.Datainterface = 1;
} catch(const std::out_of_range&) {
} catch (const std::out_of_range&) {
fifo_cfg.Datainterface = 0;
}
......
......@@ -76,7 +76,7 @@ AxiStreamSwitch::connectInternal(const std::string &portSlave,
// check if slave port exists
try {
getSlavePort(portSlave);
} catch(const std::out_of_range&) {
} catch (const std::out_of_range&) {
logger->error("Switch doesn't have a slave port named '{}'", portSlave);
return false;
}
......@@ -84,7 +84,7 @@ AxiStreamSwitch::connectInternal(const std::string &portSlave,
// check if master port exists
try {
getMasterPort(portMaster);
} catch(const std::out_of_range&) {
} catch (const std::out_of_range&) {
logger->error("Switch doesn't have a master port named '{}'", portMaster);
return false;
}
......
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