Commit 972377d0 authored by Steffen Vogel's avatar Steffen Vogel 🎅🏼
Browse files

refactor IpNode and IpCore class names

parent 8a13d8ad
Pipeline #293493 failed with stages
in 4 seconds
......@@ -42,7 +42,7 @@
#include <villas/kernel/vfio.hpp>
#include <villas/fpga/config.h>
#include <villas/fpga/ip.hpp>
#include <villas/fpga/core.hpp>
#define PCI_FILTER_DEFAULT_FPGA { \
.id = { \
......@@ -75,9 +75,9 @@ public:
bool reset() { return true; }
void dump() { }
ip::IpCore::Ptr lookupIp(const std::string& name) const;
ip::IpCore::Ptr lookupIp(const Vlnv& vlnv) const;
ip::IpCore::Ptr lookupIp(const ip::IpIdentifier& id) const;
ip::Core::Ptr lookupIp(const std::string& name) const;
ip::Core::Ptr lookupIp(const Vlnv& vlnv) const;
ip::Core::Ptr lookupIp(const ip::IpIdentifier& id) const;
bool
mapMemoryBlock(const MemoryBlock& block);
......@@ -87,7 +87,7 @@ private:
std::set<MemoryManager::AddressSpaceId> memoryBlocksMapped;
public: // TODO: make this private
ip::IpCore::List ips; ///< IPs located on this FPGA card
ip::Core::List ips; ///< IPs located on this FPGA card
bool do_reset; /**< Reset VILLASfpga during startup? */
int affinity; /**< Affinity for MSI interrupts */
......
......@@ -51,8 +51,8 @@ class PCIeCard;
namespace ip {
// forward declarations
class IpCore;
class IpCoreFactory;
class Core;
class CoreFactory;
class InterruptController;
......@@ -98,15 +98,15 @@ private:
};
class IpCore {
friend IpCoreFactory;
class Core {
friend CoreFactory;
public:
IpCore() : card(nullptr) {}
virtual ~IpCore() = default;
Core() : card(nullptr) {}
virtual ~Core() = default;
using Ptr = std::shared_ptr<IpCore>;
using List = std::list<IpCore::Ptr>;
using Ptr = std::shared_ptr<Core>;
using List = std::list<Core::Ptr>;
public:
/* Generic management interface for IPs */
......@@ -168,15 +168,15 @@ public:
{ return getInstanceName() != otherName; }
bool
operator==(const IpCore& otherIp) const
operator==(const Core& otherIp) const
{ return this->id == otherIp.id; }
bool
operator!=(const IpCore& otherIp) const
operator!=(const Core& otherIp) const
{ return this->id != otherIp.id; }
friend std::ostream&
operator<< (std::ostream& stream, const IpCore& ip)
operator<< (std::ostream& stream, const Core& ip)
{ return stream << ip.id; }
protected:
......@@ -237,12 +237,12 @@ protected:
class IpCoreFactory : public plugin::Plugin {
class CoreFactory : public plugin::Plugin {
public:
using plugin::Plugin::Plugin;
/// Returns a running and checked FPGA IP
static IpCore::List
static Core::List
make(PCIeCard* card, json_t *json_ips);
protected:
......@@ -252,20 +252,20 @@ protected:
private:
/// Create a concrete IP instance
virtual IpCore* create() = 0;
virtual Core* create() = 0;
/// Configure IP instance from JSON config
virtual bool configureJson(IpCore& /* ip */, json_t* /* json */)
virtual bool configureJson(Core& /* ip */, json_t* /* json */)
{ return true; }
virtual Vlnv getCompatibleVlnv() const = 0;
protected:
static Logger
getStaticLogger() { return villas::logging.get("IpCoreFactory"); }
getStaticLogger() { return villas::logging.get("CoreFactory"); }
private:
static IpCoreFactory*
static CoreFactory*
lookup(const Vlnv& vlnv);
};
......
......@@ -27,13 +27,13 @@
#pragma once
#include <villas/fpga/ip_node.hpp>
#include <villas/fpga/node.hpp>
namespace villas {
namespace fpga {
namespace ip {
class Aurora : public IpNode {
class Aurora : public Node {
public:
static constexpr const char* masterPort = "m_axis";
static constexpr const char* slavePort = "s_axis";
......@@ -62,10 +62,10 @@ private:
};
class AuroraFactory : public IpNodeFactory {
class AuroraFactory : public NodeFactory {
public:
IpCore* create()
Core* create()
{ return new Aurora; }
virtual std::string
......
......@@ -27,14 +27,14 @@
#pragma once
#include <villas/memory.hpp>
#include <villas/fpga/ip.hpp>
#include <villas/fpga/core.hpp>
namespace villas {
namespace fpga {
namespace ip {
class Bram : public IpCore
class Bram : public Core
{
friend class BramFactory;
public:
......@@ -56,12 +56,12 @@ private:
class BramFactory : public IpCoreFactory {
class BramFactory : public CoreFactory {
public:
bool configureJson(IpCore& ip, json_t *json_ip);
bool configureJson(Core& ip, json_t *json_ip);
IpCore* create()
Core* create()
{ return new Bram; }
virtual std::string
......
......@@ -29,13 +29,13 @@
#include <xilinx/xaxidma.h>
#include <villas/memory.hpp>
#include <villas/fpga/ip_node.hpp>
#include <villas/fpga/node.hpp>
namespace villas {
namespace fpga {
namespace ip {
class Dma : public IpNode
class Dma : public Node
{
public:
friend class DmaFactory;
......@@ -112,10 +112,10 @@ private:
class DmaFactory : public IpNodeFactory {
class DmaFactory : public NodeFactory {
public:
IpCore* create()
Core* create()
{ return new Dma; }
virtual std::string
......
......@@ -31,7 +31,7 @@
#include <xilinx/xllfifo.h>
#include <villas/fpga/ip_node.hpp>
#include <villas/fpga/node.hpp>
namespace villas {
......@@ -39,7 +39,7 @@ namespace fpga {
namespace ip {
class Fifo : public IpNode
class Fifo : public Node
{
public:
friend class FifoFactory;
......@@ -63,10 +63,10 @@ private:
class FifoFactory : public IpNodeFactory {
class FifoFactory : public NodeFactory {
public:
IpCore* create()
Core* create()
{ return new Fifo; }
std::string
......@@ -82,15 +82,15 @@ public:
};
class FifoData : public IpNode {
class FifoData : public Node {
friend class FifoDataFactory;
};
class FifoDataFactory : public IpNodeFactory {
class FifoDataFactory : public NodeFactory {
public:
IpCore* create()
Core* create()
{ return new FifoData; }
virtual std::string
......
......@@ -30,14 +30,14 @@
#include <xilinx/xintc.h>
#include <villas/fpga/ip.hpp>
#include <villas/fpga/core.hpp>
namespace villas {
namespace fpga {
namespace ip {
class GeneralPurposeIO : public IpCore
class GeneralPurposeIO : public Core
{
public:
......@@ -51,14 +51,14 @@ private:
{ return { registerMemory }; }
};
class GeneralPurposeIOFactory : public IpCoreFactory {
class GeneralPurposeIOFactory : public CoreFactory {
public:
static constexpr const char*
getCompatibleVlnvString()
{ return "xilinx.com:ip:axi_gpio:"; }
IpCore* create()
Core* create()
{ return new GeneralPurposeIO; }
virtual std::string
......
#pragma once
#include <villas/memory.hpp>
#include <villas/fpga/ip_node.hpp>
#include <villas/fpga/node.hpp>
#include <villas/fpga/ips/hls.hpp>
#include <villas/fpga/ips/rtds2gpu/register_types.hpp>
......@@ -12,7 +12,7 @@ namespace fpga {
namespace ip {
class Gpu2Rtds : public IpNode, public Hls
class Gpu2Rtds : public Node, public Hls
{
public:
friend class Gpu2RtdsFactory;
......@@ -63,10 +63,10 @@ public:
};
class Gpu2RtdsFactory : public IpNodeFactory {
class Gpu2RtdsFactory : public NodeFactory {
public:
IpCore* create()
Core* create()
{ return new Gpu2Rtds; }
virtual std::string
......
#pragma once
#include <villas/memory.hpp>
#include <villas/fpga/ip_node.hpp>
#include <villas/fpga/node.hpp>
namespace villas {
namespace fpga {
namespace ip {
class Hls : public virtual IpCore
class Hls : public virtual Core
{
public:
virtual bool init()
......
......@@ -30,14 +30,14 @@
#include <xilinx/xintc.h>
#include <villas/fpga/ip.hpp>
#include <villas/fpga/core.hpp>
namespace villas {
namespace fpga {
namespace ip {
class InterruptController : public IpCore
class InterruptController : public Core
{
public:
using IrqMaskType = uint32_t;
......@@ -81,14 +81,14 @@ private:
class InterruptControllerFactory : public IpCoreFactory {
class InterruptControllerFactory : public CoreFactory {
public:
static constexpr const char*
getCompatibleVlnvString()
{ return "acs.eonerc.rwth-aachen.de:user:axi_pcie_intc:"; }
IpCore* create()
Core* create()
{ return new InterruptController; }
virtual std::string
......
......@@ -32,13 +32,13 @@
#include <xilinx/xaxis_switch.h>
#include <villas/fpga/ip_node.hpp>
#include <villas/fpga/node.hpp>
namespace villas {
namespace fpga {
namespace ip {
class AxiPciExpressBridge : public IpCore {
class AxiPciExpressBridge : public Core {
public:
friend class AxiPciExpressBridgeFactory;
......@@ -63,16 +63,16 @@ private:
};
class AxiPciExpressBridgeFactory : public IpCoreFactory {
class AxiPciExpressBridgeFactory : public CoreFactory {
public:
static constexpr const char*
getCompatibleVlnvString()
{ return "xilinx.com:ip:axi_pcie:"; }
bool configureJson(IpCore& ip, json_t *json_ip);
bool configureJson(Core& ip, json_t *json_ip);
IpCore* create()
Core* create()
{ return new AxiPciExpressBridge; }
virtual std::string
......
......@@ -27,13 +27,13 @@
#pragma once
#include <villas/fpga/ip_node.hpp>
#include <villas/fpga/node.hpp>
namespace villas {
namespace fpga {
namespace ip {
class Rtds : public IpNode {
class Rtds : public Node {
public:
static constexpr const char* masterPort = "m_axis";
static constexpr const char* slavePort = "s_axis";
......@@ -60,9 +60,9 @@ private:
};
class RtdsFactory : public IpNodeFactory {
class RtdsFactory : public NodeFactory {
public:
IpCore* create()
Core* create()
{ return new Rtds; }
virtual std::string
......
#pragma once
#include <villas/memory.hpp>
#include <villas/fpga/ip_node.hpp>
#include <villas/fpga/node.hpp>
#include <villas/fpga/ips/hls.hpp>
#include "rtds2gpu/xrtds2gpu.h"
......@@ -25,7 +25,7 @@ union ControlRegister {
};
class Rtds2Gpu : public IpNode, public Hls
class Rtds2Gpu : public Node, public Hls
{
public:
friend class Rtds2GpuFactory;
......@@ -72,10 +72,10 @@ private:
};
class Rtds2GpuFactory : public IpNodeFactory {
class Rtds2GpuFactory : public NodeFactory {
public:
IpCore* create()
Core* create()
{ return new Rtds2Gpu; }
virtual std::string
......
......@@ -34,13 +34,13 @@
#include <xilinx/xaxis_switch.h>
#include <villas/fpga/ip_node.hpp>
#include <villas/fpga/node.hpp>
namespace villas {
namespace fpga {
namespace ip {
class AxiStreamSwitch : public IpNode {
class AxiStreamSwitch : public Node {
public:
friend class AxiStreamSwitchFactory;
......@@ -60,8 +60,8 @@ private:
{ return { registerMemory }; }
struct Path {
IpCore* masterOut;
IpCore* slaveIn;
Core* masterOut;
Core* slaveIn;
};
int num_ports;
......@@ -70,16 +70,16 @@ private:
};
class AxiStreamSwitchFactory : public IpNodeFactory {
class AxiStreamSwitchFactory : public NodeFactory {
public:
static constexpr const char*
getCompatibleVlnvString()
{ return "xilinx.com:ip:axis_switch:"; }
bool configureJson(IpCore& ip, json_t *json_ip);
bool configureJson(Core& ip, json_t *json_ip);
IpCore* create()
Core* create()
{ return new AxiStreamSwitch; }
virtual std::string
......
......@@ -33,14 +33,14 @@
#include <xilinx/xtmrctr.h>
#include <villas/fpga/config.h>
#include <villas/fpga/ip.hpp>
#include <villas/fpga/core.hpp>
namespace villas {
namespace fpga {
namespace ip {
class Timer : public IpCore
class Timer : public Core
{
friend class TimerFactory;
public:
......@@ -73,10 +73,10 @@ private:
class TimerFactory : public IpCoreFactory {
class TimerFactory : public CoreFactory {
public:
IpCore* create()
Core* create()
{ return new Timer; }
virtual std::string
......
......@@ -34,7 +34,7 @@
#include <string>
#include <jansson.h>
#include <villas/fpga/ip.hpp>
#include <villas/fpga/core.hpp>
#include <villas/graph/directed.hpp>
......@@ -85,10 +85,10 @@ public:
};
class IpNode : public virtual IpCore {
class Node : public virtual Core {
public:
friend class IpNodeFactory;
friend class NodeFactory;
struct StreamPort {
int portNumber;
......@@ -107,7 +107,7 @@ public:
// easy-usage assuming that the slave IP to connect to only has one slave
// port and implements the getDefaultSlavePort() function
bool connect(const IpNode& slaveNode)
bool connect(const Node& slaveNode)
{ return this->connect(this->getDefaultMasterPort(), slaveNode.getDefaultSlavePort()); }
// used by easy-usage connect, will throw if not implemented by derived node
......@@ -140,11 +140,11 @@ protected:
static StreamGraph streamGraph;
};
class IpNodeFactory : public IpCoreFactory {
class NodeFactory : public CoreFactory {
public:
using IpCoreFactory::IpCoreFactory;
using CoreFactory::CoreFactory;
virtual bool configureJson(IpCore& ip, json_t *json_ip);
virtual bool configureJson(Core& ip, json_t *json_ip);
};
/** @} */
......
......@@ -23,8 +23,8 @@
set(SOURCES
vlnv.cpp
card.cpp
ip.cpp
ip_node.cpp
core.cpp
node.cpp
ips/timer.cpp
ips/switch.cpp
......
......@@ -29,7 +29,7 @@
#include <villas/kernel/pci.h>
#include <villas/kernel/vfio.hpp>
#include <villas/fpga/ip.hpp>
#include <villas/fpga/core.hpp>
#include <villas/fpga/card.hpp>
namespace villas {
......@@ -92,7 +92,7 @@ PCIeCardFactory::make(json_t *json, struct pci* pci, std::shared_ptr<VfioContain
continue;
}
card->ips = ip::IpCoreFactory::make(card.get(), json_ips);
card->ips = ip::CoreFactory::make(card.get(), json_ips);
if (card->ips.empty()) {
logger->error("Cannot initialize IPs of FPGA card {}", card_name);