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VILLASframework
VILLASfpga
VILLASfpga
Commits
65263a7b
Commit
65263a7b
authored
May 30, 2018
by
Daniel Krebs
Browse files
fix wrong usage of reinterpret_cast in ips and tests
parent
4840eaa5
Changes
7
Hide whitespace changes
Inline
Side-by-side
lib/ips/bram.cpp
View file @
65263a7b
...
@@ -9,7 +9,7 @@ static BramFactory factory;
...
@@ -9,7 +9,7 @@ static BramFactory factory;
bool
bool
BramFactory
::
configureJson
(
IpCore
&
ip
,
json_t
*
json_ip
)
BramFactory
::
configureJson
(
IpCore
&
ip
,
json_t
*
json_ip
)
{
{
auto
&
bram
=
reinterpret
_cast
<
Bram
&>
(
ip
);
auto
&
bram
=
dynamic
_cast
<
Bram
&>
(
ip
);
if
(
json_unpack
(
json_ip
,
"{ s: i }"
,
"size"
,
&
bram
.
size
)
!=
0
)
{
if
(
json_unpack
(
json_ip
,
"{ s: i }"
,
"size"
,
&
bram
.
size
)
!=
0
)
{
getLogger
()
->
error
(
"Cannot parse 'size'"
);
getLogger
()
->
error
(
"Cannot parse 'size'"
);
...
...
lib/ips/pcie.cpp
View file @
65263a7b
...
@@ -125,7 +125,7 @@ bool
...
@@ -125,7 +125,7 @@ bool
AxiPciExpressBridgeFactory
::
configureJson
(
IpCore
&
ip
,
json_t
*
json_ip
)
AxiPciExpressBridgeFactory
::
configureJson
(
IpCore
&
ip
,
json_t
*
json_ip
)
{
{
auto
logger
=
getLogger
();
auto
logger
=
getLogger
();
auto
&
pcie
=
reinterpret
_cast
<
AxiPciExpressBridge
&>
(
ip
);
auto
&
pcie
=
dynamic
_cast
<
AxiPciExpressBridge
&>
(
ip
);
for
(
auto
barType
:
std
::
list
<
std
::
string
>
{
"axi_bars"
,
"pcie_bars"
})
{
for
(
auto
barType
:
std
::
list
<
std
::
string
>
{
"axi_bars"
,
"pcie_bars"
})
{
json_t
*
json_bars
=
json_object_get
(
json_ip
,
barType
.
c_str
());
json_t
*
json_bars
=
json_object_get
(
json_ip
,
barType
.
c_str
());
...
...
lib/ips/switch.cpp
View file @
65263a7b
...
@@ -143,7 +143,7 @@ AxiStreamSwitchFactory::configureJson(IpCore& ip, json_t* json_ip)
...
@@ -143,7 +143,7 @@ AxiStreamSwitchFactory::configureJson(IpCore& ip, json_t* json_ip)
auto
logger
=
getLogger
();
auto
logger
=
getLogger
();
auto
&
axiSwitch
=
reinterpret
_cast
<
AxiStreamSwitch
&>
(
ip
);
auto
&
axiSwitch
=
dynamic
_cast
<
AxiStreamSwitch
&>
(
ip
);
if
(
json_unpack
(
json_ip
,
"{ s: i }"
,
"num_ports"
,
&
axiSwitch
.
num_ports
)
!=
0
)
{
if
(
json_unpack
(
json_ip
,
"{ s: i }"
,
"num_ports"
,
&
axiSwitch
.
num_ports
)
!=
0
)
{
logger
->
error
(
"Cannot parse 'num_ports'"
);
logger
->
error
(
"Cannot parse 'num_ports'"
);
...
...
tests/dma.cpp
View file @
65263a7b
...
@@ -24,7 +24,7 @@ Test(fpga, dma, .description = "DMA")
...
@@ -24,7 +24,7 @@ Test(fpga, dma, .description = "DMA")
logger
->
info
(
"Testing {}"
,
*
ip
);
logger
->
info
(
"Testing {}"
,
*
ip
);
auto
dma
=
reinterpret
_cast
<
villas
::
fpga
::
ip
::
Dma
&>
(
*
ip
);
auto
dma
=
dynamic
_cast
<
villas
::
fpga
::
ip
::
Dma
&>
(
*
ip
);
if
(
not
dma
.
loopbackPossible
())
{
if
(
not
dma
.
loopbackPossible
())
{
logger
->
info
(
"Loopback test not possible for {}"
,
*
ip
);
logger
->
info
(
"Loopback test not possible for {}"
,
*
ip
);
...
...
tests/fifo.cpp
View file @
65263a7b
...
@@ -47,7 +47,7 @@ Test(fpga, fifo, .description = "FIFO")
...
@@ -47,7 +47,7 @@ Test(fpga, fifo, .description = "FIFO")
logger
->
info
(
"Testing {}"
,
*
ip
);
logger
->
info
(
"Testing {}"
,
*
ip
);
auto
fifo
=
reinterpret
_cast
<
villas
::
fpga
::
ip
::
Fifo
&>
(
*
ip
);
auto
fifo
=
dynamic
_cast
<
villas
::
fpga
::
ip
::
Fifo
&>
(
*
ip
);
if
(
not
fifo
.
connectLoopback
())
{
if
(
not
fifo
.
connectLoopback
())
{
continue
;
continue
;
...
...
tests/gpu.cpp
View file @
65263a7b
...
@@ -40,7 +40,7 @@ Test(fpga, gpu_dma, .description = "GPU DMA tests")
...
@@ -40,7 +40,7 @@ Test(fpga, gpu_dma, .description = "GPU DMA tests")
logger
->
info
(
"Testing {}"
,
*
ip
);
logger
->
info
(
"Testing {}"
,
*
ip
);
auto
bram
=
reinterpret
_cast
<
villas
::
fpga
::
ip
::
Bram
*>
(
ip
.
get
());
auto
bram
=
dynamic
_cast
<
villas
::
fpga
::
ip
::
Bram
*>
(
ip
.
get
());
cr_assert_not_null
(
bram
,
"Couldn't find BRAM"
);
cr_assert_not_null
(
bram
,
"Couldn't find BRAM"
);
count
++
;
count
++
;
...
...
tests/timer.cpp
View file @
65263a7b
...
@@ -46,7 +46,7 @@ Test(fpga, timer, .description = "Timer Counter")
...
@@ -46,7 +46,7 @@ Test(fpga, timer, .description = "Timer Counter")
count
++
;
count
++
;
auto
timer
=
reinterpret
_cast
<
villas
::
fpga
::
ip
::
Timer
&>
(
*
ip
);
auto
timer
=
dynamic
_cast
<
villas
::
fpga
::
ip
::
Timer
&>
(
*
ip
);
logger
->
info
(
"Test simple waiting"
);
logger
->
info
(
"Test simple waiting"
);
timer
.
start
(
timer
.
getFrequency
()
/
10
);
timer
.
start
(
timer
.
getFrequency
()
/
10
);
...
...
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