Commit 38030960 authored by Daniel Krebs's avatar Daniel Krebs
Browse files

scripts/hwdef-parse: promote fifo to stream IP and populate all switch ports

parent b234a59c
...@@ -35,6 +35,7 @@ whitelist = [ ...@@ -35,6 +35,7 @@ whitelist = [
[ 'acs.eonerc.rwth-aachen.de', 'sysgen' ], [ 'acs.eonerc.rwth-aachen.de', 'sysgen' ],
[ 'xilinx.com', 'ip', 'axi_gpio' ], [ 'xilinx.com', 'ip', 'axi_gpio' ],
[ 'xilinx.com', 'ip', 'axi_bram_ctrl' ], [ 'xilinx.com', 'ip', 'axi_bram_ctrl' ],
[ 'xilinx.com', 'ip', 'axis_data_fifo' ],
[ 'xilinx.com', 'ip', 'axi_pcie' ] [ 'xilinx.com', 'ip', 'axi_pcie' ]
] ]
...@@ -44,7 +45,6 @@ axi_converter_whitelist = [ ...@@ -44,7 +45,6 @@ axi_converter_whitelist = [
[ 'xilinx.com', 'ip', 'axis_subset_converter' ], [ 'xilinx.com', 'ip', 'axis_subset_converter' ],
[ 'xilinx.com', 'ip', 'axis_clock_converter' ], [ 'xilinx.com', 'ip', 'axis_clock_converter' ],
[ 'xilinx.com', 'ip', 'axis_register_slice' ], [ 'xilinx.com', 'ip', 'axis_register_slice' ],
[ 'xilinx.com', 'ip', 'axis_data_fifo' ],
[ 'xilinx.com', 'ip', 'axis_dwidth_converter' ], [ 'xilinx.com', 'ip', 'axis_dwidth_converter' ],
[ 'xilinx.com', 'ip', 'axis_register_slice' ] [ 'xilinx.com', 'ip', 'axis_register_slice' ]
] ]
...@@ -173,19 +173,32 @@ for busif in busifs: ...@@ -173,19 +173,32 @@ for busif in busifs:
port = int(m.group(2)) port = int(m.group(2))
switch_ip_ports = ips[switch.get('INSTANCE')].setdefault('ports', [])
ep, busname_ep = bus_trace(root, busname, opponent[type], whitelist) ep, busname_ep = bus_trace(root, busname, opponent[type], whitelist)
if ep in ips: if ep in ips:
ports = ips[ep].setdefault('ports', []) ports = ips[ep].setdefault('ports', [])
ports.append({ ports.append({
'role': opponent[type][0].lower(), 'role': opponent[type][0].lower(),
'target': '{}:{}'.format(switch.get('INSTANCE'), port) 'target': '{}:{}'.format(switch.get('INSTANCE'), name)
}) })
module_ep = root.find('.//MODULE[@INSTANCE="{}"]'.format(ep)) module_ep = root.find('.//MODULE[@INSTANCE="{}"]'.format(ep))
busif_ep = module_ep.find('.//BUSINTERFACE[@BUSNAME="{}"]'.format(busname_ep)) busif_ep = module_ep.find('.//BUSINTERFACE[@BUSNAME="{}"]'.format(busname_ep))
if busif_ep: if not busif_ep:
ports[-1]['name'] = sanitize_name(busif_ep.get('NAME')) print("cannot find businterface: {}".format(busname_ep))
sys.exit(1)
busif_name = ports[-1]['name'] = sanitize_name(busif_ep.get('NAME'))
ports[-1]['name'] = busif_name
switch_ip_ports.append({
'role': type.lower(),
'target': '{}:{}'.format(ep, busif_name),
'name': name
})
# set number of master/slave port pairs for switch # set number of master/slave port pairs for switch
ips[switch.get('INSTANCE')]['num_ports'] = int(switch_ports / 2) ips[switch.get('INSTANCE')]['num_ports'] = int(switch_ports / 2)
......
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