switch.cpp 4.25 KB
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/** AXI Stream interconnect related helper functions
 *
 * These functions present a simpler interface to Xilinx' AXI Stream switch driver (XAxis_Switch_*)
 *
 * @author Steffen Vogel <stvogel@eonerc.rwth-aachen.de>
 * @author Daniel Krebs <github@daniel-krebs.net>
 * @copyright 2017, Steffen Vogel
 * @license GNU General Public License (version 3)
 *
 * VILLASfpga
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 *********************************************************************************/

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#include <jansson.h>
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#include <xilinx/xaxis_switch.h>

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#include <villas/fpga/ips/switch.hpp>
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namespace villas {
namespace fpga {
namespace ip {

static AxiStreamSwitchFactory factory;

bool
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AxiStreamSwitch::init()
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{	
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	/* Setup AXI-stream switch */
	XAxis_Switch_Config sw_cfg;
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	sw_cfg.MaxNumMI = num_ports;
	sw_cfg.MaxNumSI = num_ports;
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	if(XAxisScr_CfgInitialize(&xSwitch, &sw_cfg, getBaseAddr(registerMemory)) != XST_SUCCESS) {
		logger->error("Cannot initialize switch");
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		return false;
	}

	/* Disable all masters */
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	XAxisScr_RegUpdateDisable(&xSwitch);
	XAxisScr_MiPortDisableAll(&xSwitch);
	XAxisScr_RegUpdateEnable(&xSwitch);
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	for(auto& [masterName, masterPort] : portsMaster) {

		// initialize internal mapping
		portMapping[masterName] = PORT_DISABLED;

		// each slave port may be internally routed to a master port
		for(auto& [slaveName, slavePort] : portsSlave) {
			(void) slaveName;

			streamGraph.addDefaultEdge(slavePort->getIdentifier(),
			                           masterPort->getIdentifier());
		}
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	}

	return true;
}

bool
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AxiStreamSwitch::connectInternal(const std::string& portSlave,
                                 const std::string& portMaster)
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{
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	// check if slave port exists
	try {
		getSlavePort(portSlave);
	} catch(const std::out_of_range&) {
		logger->error("Switch doesn't have a slave port named '{}'", portSlave);
		return false;
	}

	// check if master port exists
	try {
		getMasterPort(portMaster);
	} catch(const std::out_of_range&) {
		logger->error("Switch doesn't have a master port named '{}'", portMaster);
		return false;
	}

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	if(portSlave.substr(0, 1) != "S" or
	   portMaster.substr(0, 1) != "M") {
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		logger->error("sanity check failed: master {} slave {}",
		              portMaster, portSlave);
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		return false;
	}

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	if(portMapping[portMaster] == portSlave) {
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		logger->debug("Ports already connected (slave {} to master {}",
		              portSlave, portMaster);
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		return true;
	}

	for(auto [master, slave] : portMapping) {
		if(slave == portSlave) {
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			logger->warn("Slave {} has already been connected to master {}. "
			             "Disabling master {}.",
			             slave, master, master);
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			XAxisScr_RegUpdateDisable(&xSwitch);
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			XAxisScr_MiPortDisable(&xSwitch, portNameToNum(master));
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			XAxisScr_RegUpdateEnable(&xSwitch);
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			portMapping[master] = PORT_DISABLED;
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		}
	}

	/* Reconfigure switch */
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	XAxisScr_RegUpdateDisable(&xSwitch);
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	XAxisScr_MiPortEnable(&xSwitch, portNameToNum(portMaster), portNameToNum(portSlave));
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	XAxisScr_RegUpdateEnable(&xSwitch);
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	portMapping[portMaster] = portSlave;
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	logger->debug("Connect slave {} to master {}", portSlave, portMaster);
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	return true;
}

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int
AxiStreamSwitch::portNameToNum(const std::string& portName)
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{
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	const std::string number = portName.substr(1, 2);
	return std::stoi(number);
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}

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bool
AxiStreamSwitchFactory::configureJson(IpCore& ip, json_t* json_ip)
{
	if(not IpNodeFactory::configureJson(ip, json_ip))
		return false;

	auto logger = getLogger();

	auto& axiSwitch = reinterpret_cast<AxiStreamSwitch&>(ip);

	if(json_unpack(json_ip, "{ s: i }", "num_ports", &axiSwitch.num_ports) != 0) {
		logger->error("Cannot parse 'num_ports'");
		return false;
	}

	return true;
}


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} // namespace ip
} // namespace fpga
} // namespace villas