Commit a87df1b5 authored by Steffen Vogel's avatar Steffen Vogel 🎅🏼

Merge branch 'feature/hls-rtds2gpu' into develop

parents 86fab248 90cb9374
Subproject commit dd7d75d0aab3801d65f9ff757d82f47f705514af
Subproject commit 9747c6ead6dedff943dbf22ce74e40e9b2622514
......@@ -33,12 +33,30 @@
"hier_0_axi_dma_axi_dma_0": {
"vlnv": "xilinx.com:ip:axi_dma:7.1",
"memory-view": {
"M_AXI_SG": {
"bram_0_axi_bram_ctrl_0": {
"Mem0": {
"M_AXI_MM2S": {
"pcie_0_axi_pcie_0": {
"BAR0": {
"baseaddr": 0,
"highaddr": 4294967295,
"size": 4294967296
}
}
},
"M_AXI_S2MM": {
"pcie_0_axi_pcie_0": {
"BAR0": {
"baseaddr": 0,
"highaddr": 4294967295,
"size": 4294967296
}
}
},
"M_AXI_SG": {
"hier_0_axi_dma_axi_dma_0": {
"Reg": {
"baseaddr": 4096,
"highaddr": 8191,
"size": 8192
"size": 4096
}
},
"hier_0_axi_dma_axi_dma_1": {
......@@ -48,37 +66,23 @@
"size": 4096
}
},
"hier_0_axi_dma_axi_dma_0": {
"Reg": {
"hier_0_axi_fifo_mm_s_0": {
"Mem0": {
"baseaddr": 12288,
"highaddr": 16383,
"size": 4096
}
},
"timer_0_axi_timer_0": {
"Reg": {
},
"Mem1": {
"baseaddr": 16384,
"highaddr": 20479,
"size": 4096
}
},
"hier_0_axis_interconnect_0_axis_interconnect_0_xbar": {
"Reg": {
"baseaddr": 20480,
"highaddr": 24575,
"size": 4096
"size": 8192
}
},
"hier_0_axi_fifo_mm_s_0": {
"Mem0": {
"pcie_0_axi_pcie_intc_0": {
"Reg": {
"baseaddr": 24576,
"highaddr": 28671,
"size": 4096
},
"Mem1": {
"baseaddr": 49152,
"highaddr": 57343,
"size": 8192
}
},
"pcie_0_axi_reset_0": {
......@@ -88,8 +92,8 @@
"size": 4096
}
},
"hier_0_rtds_axis_0": {
"reg0": {
"timer_0_axi_timer_0": {
"Reg": {
"baseaddr": 32768,
"highaddr": 36863,
"size": 4096
......@@ -102,13 +106,41 @@
"size": 4096
}
},
"pcie_0_axi_pcie_intc_0": {
"hier_0_rtds_axis_0": {
"reg0": {
"baseaddr": 40960,
"highaddr": 45055,
"size": 4096
}
},
"hier_0_axis_interconnect_0_axis_interconnect_0_xbar": {
"Reg": {
"baseaddr": 45056,
"highaddr": 49151,
"size": 4096
}
},
"bram_0_axi_bram_ctrl_0": {
"Mem0": {
"baseaddr": 49152,
"highaddr": 57343,
"size": 8192
}
},
"hier_0_rtds2gpu_0": {
"Reg": {
"baseaddr": 57344,
"highaddr": 61439,
"size": 4096
}
},
"hier_0_gpu2rtds_0": {
"Reg": {
"baseaddr": 61440,
"highaddr": 65535,
"size": 4096
}
},
"pcie_0_axi_pcie_0": {
"CTL0": {
"baseaddr": 268435456,
......@@ -116,35 +148,17 @@
"size": 268435456
}
}
},
"M_AXI_MM2S": {
"pcie_0_axi_pcie_0": {
"BAR0": {
"baseaddr": 0,
"highaddr": 4294967295,
"size": 4294967296
}
}
},
"M_AXI_S2MM": {
"pcie_0_axi_pcie_0": {
"BAR0": {
"baseaddr": 0,
"highaddr": 4294967295,
"size": 4294967296
}
}
}
},
"ports": [
{
"role": "master",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:1",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S01_AXIS",
"name": "MM2S"
},
{
"role": "slave",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:1",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M01_AXIS",
"name": "S2MM"
}
],
......@@ -178,12 +192,12 @@
"ports": [
{
"role": "master",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:6",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S06_AXIS",
"name": "MM2S"
},
{
"role": "slave",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:6",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M06_AXIS",
"name": "S2MM"
}
],
......@@ -197,12 +211,12 @@
"ports": [
{
"role": "master",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:2",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S02_AXIS",
"name": "STR_TXD"
},
{
"role": "slave",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:2",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M02_AXIS",
"name": "STR_RXD"
}
],
......@@ -210,43 +224,143 @@
"interrupt": "pcie_0_axi_pcie_intc_0:2"
}
},
"hier_0_axis_data_fifo_0": {
"vlnv": "xilinx.com:ip:axis_data_fifo:1.1",
"ports": [
{
"role": "master",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S03_AXIS",
"name": "AXIS"
},
{
"role": "slave",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M03_AXIS",
"name": "AXIS"
}
]
},
"hier_0_axis_data_fifo_1": {
"vlnv": "xilinx.com:ip:axis_data_fifo:1.1",
"ports": [
{
"role": "master",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S04_AXIS",
"name": "AXIS"
},
{
"role": "slave",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M04_AXIS",
"name": "AXIS"
}
]
},
"hier_0_axis_interconnect_0_axis_interconnect_0_xbar": {
"vlnv": "xilinx.com:ip:axis_switch:1.1",
"ports": [
{
"role": "slave",
"target": "hier_0_rtds_axis_0:m_axis",
"name": "S00_AXIS"
},
{
"role": "master",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:3",
"name": "M03_AXIS"
"target": "hier_0_rtds_axis_0:s_axis",
"name": "M00_AXIS"
},
{
"role": "slave",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:3",
"target": "hier_0_axi_dma_axi_dma_0:MM2S",
"name": "S01_AXIS"
},
{
"role": "master",
"target": "hier_0_axi_dma_axi_dma_0:S2MM",
"name": "M01_AXIS"
},
{
"role": "slave",
"target": "hier_0_axi_fifo_mm_s_0:STR_TXD",
"name": "S02_AXIS"
},
{
"role": "master",
"target": "hier_0_axi_fifo_mm_s_0:STR_RXD",
"name": "M02_AXIS"
},
{
"role": "slave",
"target": "hier_0_axis_data_fifo_0:AXIS",
"name": "S03_AXIS"
},
{
"role": "master",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:4",
"name": "M04_AXIS"
"target": "hier_0_axis_data_fifo_0:AXIS",
"name": "M03_AXIS"
},
{
"role": "slave",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:4",
"target": "hier_0_axis_data_fifo_1:AXIS",
"name": "S04_AXIS"
},
{
"role": "master",
"target": "hier_0_axis_data_fifo_1:AXIS",
"name": "M04_AXIS"
},
{
"role": "slave",
"target": "hier_0_hls_dft_0:output_r",
"name": "S05_AXIS"
},
{
"role": "master",
"target": "hier_0_hls_dft_0:input_r",
"name": "M05_AXIS"
},
{
"role": "slave",
"target": "hier_0_axi_dma_axi_dma_1:MM2S",
"name": "S06_AXIS"
},
{
"role": "master",
"target": "hier_0_axi_dma_axi_dma_1:S2MM",
"name": "M06_AXIS"
},
{
"role": "slave",
"target": "hier_0_gpu2rtds_0:rtds_output",
"name": "S07_AXIS"
},
{
"role": "master",
"target": "hier_0_rtds2gpu_0:rtds_input",
"name": "M07_AXIS"
}
],
"num_ports": 7
"num_ports": 8
},
"hier_0_gpu2rtds_0": {
"vlnv": "acs.eonerc.rwth-aachen.de:hls:gpu2rtds:1.0",
"ports": [
{
"role": "master",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S07_AXIS",
"name": "rtds_output"
}
]
},
"hier_0_hls_dft_0": {
"vlnv": "acs.eonerc.rwth-aachen.de:hls:hls_dft:1.1",
"ports": [
{
"role": "master",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:5",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S05_AXIS",
"name": "output_r"
},
{
"role": "slave",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:5",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M05_AXIS",
"name": "input_r"
}
],
......@@ -254,17 +368,38 @@
"interrupt": "pcie_0_axi_pcie_intc_0:1"
}
},
"hier_0_rtds2gpu_0": {
"vlnv": "acs.eonerc.rwth-aachen.de:hls:rtds2gpu:1.1",
"memory-view": {
"m_axi_axi_mm": {
"pcie_0_axi_pcie_0": {
"BAR0": {
"baseaddr": 0,
"highaddr": 4294967295,
"size": 4294967296
}
}
}
},
"ports": [
{
"role": "slave",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M07_AXIS",
"name": "rtds_input"
}
]
},
"hier_0_rtds_axis_0": {
"vlnv": "acs.eonerc.rwth-aachen.de:user:rtds_axis:1.0",
"ports": [
{
"role": "master",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:0",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:S00_AXIS",
"name": "m_axis"
},
{
"role": "slave",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:0",
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:M00_AXIS",
"name": "s_axis"
}
],
......@@ -278,11 +413,11 @@
"vlnv": "xilinx.com:ip:axi_pcie:2.8",
"memory-view": {
"M_AXI": {
"bram_0_axi_bram_ctrl_0": {
"Mem0": {
"baseaddr": 0,
"hier_0_axi_dma_axi_dma_0": {
"Reg": {
"baseaddr": 4096,
"highaddr": 8191,
"size": 8192
"size": 4096
}
},
"hier_0_axi_dma_axi_dma_1": {
......@@ -292,37 +427,23 @@
"size": 4096
}
},
"hier_0_axi_dma_axi_dma_0": {
"Reg": {
"hier_0_axi_fifo_mm_s_0": {
"Mem0": {
"baseaddr": 12288,
"highaddr": 16383,
"size": 4096
}
},
"timer_0_axi_timer_0": {
"Reg": {
},
"Mem1": {
"baseaddr": 16384,
"highaddr": 20479,
"size": 4096
}
},
"hier_0_axis_interconnect_0_axis_interconnect_0_xbar": {
"Reg": {
"baseaddr": 20480,
"highaddr": 24575,
"size": 4096
"size": 8192
}
},
"hier_0_axi_fifo_mm_s_0": {
"Mem0": {
"pcie_0_axi_pcie_intc_0": {
"Reg": {
"baseaddr": 24576,
"highaddr": 28671,
"size": 4096
},
"Mem1": {
"baseaddr": 49152,
"highaddr": 57343,
"size": 8192
}
},
"pcie_0_axi_reset_0": {
......@@ -332,8 +453,8 @@
"size": 4096
}
},
"hier_0_rtds_axis_0": {
"reg0": {
"timer_0_axi_timer_0": {
"Reg": {
"baseaddr": 32768,
"highaddr": 36863,
"size": 4096
......@@ -346,13 +467,41 @@
"size": 4096
}
},
"pcie_0_axi_pcie_intc_0": {
"hier_0_rtds_axis_0": {
"reg0": {
"baseaddr": 40960,
"highaddr": 45055,
"size": 4096
}
},
"hier_0_axis_interconnect_0_axis_interconnect_0_xbar": {
"Reg": {
"baseaddr": 45056,
"highaddr": 49151,
"size": 4096
}
},
"bram_0_axi_bram_ctrl_0": {
"Mem0": {
"baseaddr": 49152,
"highaddr": 57343,
"size": 8192
}
},
"hier_0_rtds2gpu_0": {
"Reg": {
"baseaddr": 57344,
"highaddr": 61439,
"size": 4096
}
},
"hier_0_gpu2rtds_0": {
"Reg": {
"baseaddr": 61440,
"highaddr": 65535,
"size": 4096
}
},
"pcie_0_axi_pcie_0": {
"CTL0": {
"baseaddr": 268435456,
......
......@@ -71,8 +71,8 @@ public:
const std::string& port,
bool isMaster)
{
for(auto& [vertexId, vertex] : vertices) {
(void) vertexId;
for(auto& vertexEntry : vertices) {
auto& vertex = vertexEntry.second;
if(vertex->nodeName == node and vertex->portName == port and vertex->isMaster == isMaster)
return vertex;
}
......@@ -86,7 +86,7 @@ public:
};
class IpNode : public IpCore {
class IpNode : public virtual IpCore {
public:
friend class IpNodeFactory;
......
......@@ -43,7 +43,10 @@ public:
bool init();
bool reset();
// memory-mapped to stream (MM2S)
bool write(const MemoryBlock& mem, size_t len);
// stream to memory-mapped (S2MM)
bool read(const MemoryBlock& mem, size_t len);
size_t writeComplete()
......
#pragma once
#include <villas/memory.hpp>
#include <villas/fpga/ip_node.hpp>
#include <villas/fpga/ips/hls.hpp>
#include <villas/fpga/ips/rtds2gpu/register_types.hpp>
#include <villas/fpga/ips/rtds2gpu/xgpu2rtds_hw.h>
namespace villas {
namespace fpga {
namespace ip {
class Gpu2Rtds : public IpNode, public Hls
{
public:
friend class Gpu2RtdsFactory;
bool init();
void dump(spdlog::level::level_enum logLevel = spdlog::level::info);
bool startOnce(size_t frameSize);
size_t getMaxFrameSize();
const StreamVertex&
getDefaultMasterPort() const
{ return getMasterPort(rtdsOutputStreamPort); }
MemoryBlock
getRegisterMemory() const
{ return MemoryBlock(0, 1 << 10, getAddressSpaceId(registerMemory)); }
private:
bool updateStatus();
public:
static constexpr const char* rtdsOutputStreamPort = "rtds_output";
struct StatusControlRegister { uint32_t
status_ap_vld : 1,
_res : 31;
};
using StatusRegister = axilite_reg_status_t;
static constexpr uintptr_t registerStatusOffset = XGPU2RTDS_CTRL_ADDR_STATUS_DATA;
static constexpr uintptr_t registerStatusCtrlOffset = XGPU2RTDS_CTRL_ADDR_STATUS_CTRL;
static constexpr uintptr_t registerFrameSizeOffset = XGPU2RTDS_CTRL_ADDR_FRAME_SIZE_DATA;
static constexpr uintptr_t registerFrameOffset = XGPU2RTDS_CTRL_ADDR_FRAME_BASE;
static constexpr uintptr_t registerFrameLength = XGPU2RTDS_CTRL_DEPTH_FRAME;
public:
StatusRegister* registerStatus;
StatusControlRegister* registerStatusCtrl;
uint32_t* registerFrameSize;
uint32_t* registerFrames;
size_t maxFrameSize;
bool started;
};
class Gpu2RtdsFactory : public IpNodeFactory {
public:
Gpu2RtdsFactory();
IpCore* create()
{ return new Gpu2Rtds; }
std::string
getName() const
{ return "Gpu2Rtds"; }
std::string
getDescription() const
{ return "HLS Gpu2Rtds IP"; }
Vlnv getCompatibleVlnv() const
{ return {"acs.eonerc.rwth-aachen.de:hls:gpu2rtds:"}; }
};
} // namespace ip
} // namespace fpga
} // namespace villas
#pragma once
#include <villas/memory.hpp>
#include <villas/fpga/ip_node.hpp>
namespace villas {
namespace fpga {
namespace ip {
class Hls : public virtual IpCore
{
public:
virtual bool init()
{
auto& registers = addressTranslations.at(registerMemory);
controlRegister = reinterpret_cast<ControlRegister*>(registers.getLocalAddr(registerControlAddr));
globalIntRegister = reinterpret_cast<GlobalIntRegister*>(registers.getLocalAddr(registerGlobalIntEnableAddr));
ipIntEnableRegister = reinterpret_cast<IpIntRegister*>(registers.getLocalAddr(registerIntEnableAddr));
ipIntStatusRegister = reinterpret_cast<IpIntRegister*>(registers.getLocalAddr(registerIntStatusAddr));
setAutoRestart(false);
setGlobalInterrupt(false);
return true;
}
bool start()
{
controlRegister->ap_start = true;
running = true;
return true;
}
virtual bool isFinished()
{ updateRunningStatus(); return !running; }
bool isRunning()
{ updateRunningStatus(); return running; }
void setAutoRestart(bool enabled) const
{ controlRegister->auto_restart = enabled; }
void setGlobalInterrupt(bool enabled) const
{ globalIntRegister->globalInterruptEnable = enabled; }
void setReadyInterrupt(bool enabled) const
{ ipIntEnableRegister->ap_ready = enabled; }
void setDoneInterrupt(bool enabled) const
{ ipIntEnableRegister->ap_done = enabled; }
bool isIdleBit() const
{ return controlRegister->ap_idle; }
bool isReadyBit() const
{ return controlRegister->ap_ready; }
/// Warning: the corresponding bit is cleared on read of the register, so if
/// not used correctly, this function may never return true. Only use this
/// function if you really know what you are doing!
bool isDoneBit() const
{ return controlRegister->ap_done; }
bool isAutoRestartBit() const
{ return controlRegister->auto_restart; }
private:
void updateRunningStatus()
{
if(running and isIdleBit())
running = false;
}
protected:
/* Memory block handling */
static constexpr const char* registerMemory = "Reg";
virtual std::list<MemoryBlockName> getMemoryBlocks() const
{ return { registerMemory }; }
public:
/* Register definitions */
static constexpr uintptr_t registerControlAddr = 0x00;
static constexpr uintptr_t registerGlobalIntEnableAddr = 0x04;
static constexpr uintptr_t registerIntEnableAddr = 0x08;
static constexpr uintptr_t registerIntStatusAddr = 0x0c;
union ControlRegister {
uint32_t value;