Commit a69af4d1 authored by Daniel Krebs's avatar Daniel Krebs

hwdef-parse: follow OR-gate merging DMA interrupts

Also update JSON config with the new output.
parent f3c765be
......@@ -147,7 +147,11 @@
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:1",
"name": "S2MM"
}
]
],
"irqs": {
"mm2s_introut": "pcie_0_axi_pcie_intc_0:3",
"s2mm_introut": "pcie_0_axi_pcie_intc_0:4"
}
},
"hier_0_axi_dma_axi_dma_1": {
"vlnv": "xilinx.com:ip:axi_dma:7.1",
......@@ -182,7 +186,11 @@
"target": "hier_0_axis_interconnect_0_axis_interconnect_0_xbar:6",
"name": "S2MM"
}
]
],
"irqs": {
"mm2s_introut": "pcie_0_axi_pcie_intc_0:3",
"s2mm_introut": "pcie_0_axi_pcie_intc_0:4"
}
},
"hier_0_axi_fifo_mm_s_0": {
"vlnv": "xilinx.com:ip:axi_fifo_mm_s:4.1",
......
......@@ -200,7 +200,7 @@ ports = concat.xpath('.//PORT[@DIR="I"]')
for port in ports:
name = port.get('NAME')
signame = port.get('SIGNAME')
# Skip unconnected IRQs
if not signame:
continue
......@@ -213,13 +213,34 @@ for port in ports:
instance = ip.get('INSTANCE')
vlnv = ip.get('VLNV')
modtype = ip.get('MODTYPE')
originators = []
# follow one level of OR gates merging interrupts (may be generalized later)
if modtype == 'util_vector_logic':
logic_op = ip.xpath('.//PARAMETER[@NAME="C_OPERATION"]')[0]
if logic_op.get('VALUE') == 'or':
# hardware interrupts sharing the same IRQ at the controller
ports = ip.xpath('.//PORT[@DIR="I"]')
for port in ports:
signame = port.get('SIGNAME')
ip = root.xpath('.//MODULE[.//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(signame))[0]
instance = ip.get('INSTANCE')
originators.append((instance, signame))
else:
# consider this instance as originator
originators.append((instance, signame))
port = ip.xpath('.//PORT[@SIGNAME="{}" and @DIR="O"]'.format(signame))[0]
irqname = port.get('NAME')
if instance in ips:
irqs = ips[instance].setdefault('irqs', {})
irqs[irqname] = '{}:{}'.format(intc.get('INSTANCE'), irq)
for instance, signame in originators:
ip = root.xpath('.//MODULE[.//PORT[@SIGNAME="{}" and @DIR="O"]]'.format(signame))[0]
port = ip.xpath('.//PORT[@SIGNAME="{}" and @DIR="O"]'.format(signame))[0]
irqname = port.get('NAME')
if instance in ips:
irqs = ips[instance].setdefault('irqs', {})
irqs[irqname] = '{}:{}'.format(intc.get('INSTANCE'), irq)
# Find BRAM storage depths (size)
brams = root.xpath('.//MODULE[@MODTYPE="axi_bram_ctrl"]')
......
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