Commit 9263d3a1 authored by Daniel Krebs's avatar Daniel Krebs

rtds2gpu: update to v1.2 bitstream

Now supports 64 words per frame
parent be5f56f6
Pipeline #73344 failed with stages
in 5 minutes and 55 seconds
......@@ -341,7 +341,7 @@
"num_ports": 8
},
"hier_0_gpu2rtds_0": {
"vlnv": "acs.eonerc.rwth-aachen.de:hls:gpu2rtds:1.0",
"vlnv": "acs.eonerc.rwth-aachen.de:hls:gpu2rtds:1.2",
"ports": [
{
"role": "master",
......@@ -369,7 +369,7 @@
}
},
"hier_0_rtds2gpu_0": {
"vlnv": "acs.eonerc.rwth-aachen.de:hls:rtds2gpu:1.1",
"vlnv": "acs.eonerc.rwth-aachen.de:hls:rtds2gpu:1.2",
"memory-view": {
"m_axi_axi_mm": {
"pcie_0_axi_pcie_0": {
......
......@@ -19,6 +19,29 @@ union axilite_reg_status_t {
};
};
/*
* Access functions for status register to handle offset in register
* representation because of size constraints.
*/
static inline void
setStatusMaxFrameSize(volatile axilite_reg_status_t& reg, uint32_t value)
{ reg.max_frame_size = value - 1; }
static inline void
setStatusLastCount(volatile axilite_reg_status_t& reg, uint32_t value)
{ reg.last_count = value - 1; }
static inline uint32_t
getStatusLastCount(const volatile axilite_reg_status_t& reg)
{ return reg.last_count + 1; }
static inline uint32_t
getStatusMaxFrameSize(const volatile axilite_reg_status_t& reg)
{ return reg.max_frame_size + 1; }
union reg_doorbell_t {
uint32_t value;
struct {
......@@ -31,6 +54,24 @@ union reg_doorbell_t {
constexpr reg_doorbell_t() : value(0) {}
};
/*
* Access functions for doorbell register to handle offset in register
* representation because of size constraints.
*/
static inline void
setDoorbellCount(volatile reg_doorbell_t& reg, uint32_t value)
{ reg.count = value - 1; }
static inline uint32_t
getDoorbellCount(const volatile reg_doorbell_t& reg)
{ return reg.count + 1; }
template<size_t N, typename T = uint32_t>
struct Rtds2GpuMemoryBuffer {
// this type is only for memory interpretation, it makes no sense to create
......
......@@ -6,48 +6,48 @@
// ==============================================================
// CTRL
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x10 : Data signal of frame_size
// bit 31~0 - frame_size[31:0] (Read/Write)
// 0x14 : reserved
// 0x80 : Data signal of status
// bit 31~0 - status[31:0] (Read)
// 0x84 : Control signal of status
// bit 0 - status_ap_vld (Read/COR)
// others - reserved
// 0x40 ~
// 0x7f : Memory 'frame' (16 * 32b)
// Word n : bit [31:0] - frame[n]
// 0x000 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x004 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x008 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x00c : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x010 : Data signal of frame_size
// bit 31~0 - frame_size[31:0] (Read/Write)
// 0x014 : reserved
// 0x200 : Data signal of status
// bit 31~0 - status[31:0] (Read)
// 0x204 : Control signal of status
// bit 0 - status_ap_vld (Read/COR)
// others - reserved
// 0x100 ~
// 0x1ff : Memory 'frame' (64 * 32b)
// Word n : bit [31:0] - frame[n]
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
#define XGPU2RTDS_CTRL_ADDR_AP_CTRL 0x00
#define XGPU2RTDS_CTRL_ADDR_GIE 0x04
#define XGPU2RTDS_CTRL_ADDR_IER 0x08
#define XGPU2RTDS_CTRL_ADDR_ISR 0x0c
#define XGPU2RTDS_CTRL_ADDR_FRAME_SIZE_DATA 0x10
#define XGPU2RTDS_CTRL_ADDR_AP_CTRL 0x000
#define XGPU2RTDS_CTRL_ADDR_GIE 0x004
#define XGPU2RTDS_CTRL_ADDR_IER 0x008
#define XGPU2RTDS_CTRL_ADDR_ISR 0x00c
#define XGPU2RTDS_CTRL_ADDR_FRAME_SIZE_DATA 0x010
#define XGPU2RTDS_CTRL_BITS_FRAME_SIZE_DATA 32
#define XGPU2RTDS_CTRL_ADDR_STATUS_DATA 0x80
#define XGPU2RTDS_CTRL_ADDR_STATUS_DATA 0x200
#define XGPU2RTDS_CTRL_BITS_STATUS_DATA 32
#define XGPU2RTDS_CTRL_ADDR_STATUS_CTRL 0x84
#define XGPU2RTDS_CTRL_ADDR_FRAME_BASE 0x40
#define XGPU2RTDS_CTRL_ADDR_FRAME_HIGH 0x7f
#define XGPU2RTDS_CTRL_ADDR_STATUS_CTRL 0x204
#define XGPU2RTDS_CTRL_ADDR_FRAME_BASE 0x100
#define XGPU2RTDS_CTRL_ADDR_FRAME_HIGH 0x1ff
#define XGPU2RTDS_CTRL_WIDTH_FRAME 32
#define XGPU2RTDS_CTRL_DEPTH_FRAME 16
#define XGPU2RTDS_CTRL_DEPTH_FRAME 64
......@@ -51,9 +51,9 @@ void Gpu2Rtds::dump(spdlog::level::level_enum logLevel)
logger->log(logLevel, " Frame too short: {}", (status.frame_too_short ? "yes" : "no"));
logger->log(logLevel, " Frame too long: {}", (status.frame_too_long ? "yes" : "no"));
logger->log(logLevel, " Frame size invalid: {}", (status.invalid_frame_size ? "yes" : "no"));
logger->log(logLevel, " Last count: {}", status.last_count);
logger->log(logLevel, " Last count: {}", getStatusLastCount(status));
logger->log(logLevel, " Last seq. number: {}", status.last_seq_nr);
logger->log(logLevel, " Max. frame size: {}", status.max_frame_size);
logger->log(logLevel, " Max. frame size: {}", getStatusMaxFrameSize(status));
}
//bool Gpu2Rtds::startOnce(const MemoryBlock& mem, size_t frameSize, size_t dataOffset, size_t doorbellOffset)
......@@ -118,7 +118,7 @@ Gpu2Rtds::getMaxFrameSize()
// assert(status.max_frame_size == (*registerStatus).max_frame_size);
return status.max_frame_size;
return getStatusMaxFrameSize(status);
}
//void
......
......@@ -23,7 +23,7 @@ bool Rtds2Gpu::init()
started = false;
// maxFrameSize = getMaxFrameSize();
maxFrameSize = 16;
maxFrameSize = 64;
logger->info("Max. frame size supported: {}", maxFrameSize);
return true;
......@@ -48,9 +48,9 @@ void Rtds2Gpu::dump(spdlog::level::level_enum logLevel)
logger->log(logLevel, " Frame too short: {}", (status.frame_too_short ? "yes" : "no"));
logger->log(logLevel, " Frame too long: {}", (status.frame_too_long ? "yes" : "no"));
logger->log(logLevel, " Frame size invalid: {}", (status.invalid_frame_size ? "yes" : "no"));
logger->log(logLevel, " Last count: {}", status.last_count);
logger->log(logLevel, " Last count: {}", getStatusLastCount(status));
logger->log(logLevel, " Last seq. number: {}", status.last_seq_nr);
logger->log(logLevel, " Max. frame size: {}", status.max_frame_size);
logger->log(logLevel, " Max. frame size: {}", getStatusMaxFrameSize(status));
}
bool Rtds2Gpu::startOnce(const MemoryBlock& mem, size_t frameSize, size_t dataOffset, size_t doorbellOffset)
......@@ -107,7 +107,7 @@ Rtds2Gpu::getMaxFrameSize()
while(not isFinished());
updateStatus();
return status.max_frame_size;
return getStatusMaxFrameSize(status);
}
void
......@@ -117,7 +117,7 @@ Rtds2Gpu::dumpDoorbell(uint32_t doorbellRegister) const
logger->info("Doorbell register: {:#08x}", doorbell.value);
logger->info(" Valid: {}", (doorbell.is_valid ? "yes" : "no"));
logger->info(" Count: {}", doorbell.count);
logger->info(" Count: {}", getDoorbellCount(doorbell));
logger->info(" Seq. number: {}", doorbell.seq_nr);
}
......
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