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VILLASframework
VILLASfpga
Commits
6d9e688c
Commit
6d9e688c
authored
Sep 15, 2018
by
Daniel Krebs
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rtds2gpu: expose status register
parent
17b0679b
Pipeline
#73443
failed with stages
in 3 minutes and 25 seconds
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1
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include/villas/fpga/ips/rtds2gpu.hpp
include/villas/fpga/ips/rtds2gpu.hpp
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include/villas/fpga/ips/rtds2gpu.hpp
View file @
6d9e688c
...
...
@@ -43,6 +43,10 @@ public:
bool
doorbellIsValid
(
const
uint32_t
&
doorbellRegister
)
const
{
return
reinterpret_cast
<
const
reg_doorbell_t
&>
(
doorbellRegister
).
is_valid
;
}
const
axilite_reg_status_t
&
getStatusRegister
()
{
updateStatus
();
return
status
;
}
void
doorbellReset
(
uint32_t
&
doorbellRegister
)
const
{
doorbellRegister
=
0
;
}
...
...
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