Commit 5e3f1ccc authored by Daniel Krebs's avatar Daniel Krebs

enable -Wall, -Wextra and -Werror and fix new errors (fixes #20)

parent 1ee36fac
Pipeline #38509 failed with stages
in 41 seconds
...@@ -5,6 +5,7 @@ project(VILLASfpga C CXX) ...@@ -5,6 +5,7 @@ project(VILLASfpga C CXX)
set(CMAKE_MODULE_PATH ${CMAKE_CURRENT_LIST_DIR}/cmake) set(CMAKE_MODULE_PATH ${CMAKE_CURRENT_LIST_DIR}/cmake)
set (CMAKE_CXX_STANDARD 17) set (CMAKE_CXX_STANDARD 17)
set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -Wextra -Werror")
include_directories(thirdparty/spdlog/include) include_directories(thirdparty/spdlog/include)
......
...@@ -97,6 +97,7 @@ DependencyGraph<T>::getEvaluationOrder() const ...@@ -97,6 +97,7 @@ DependencyGraph<T>::getEvaluationOrder() const
if(added == 0 and graph.size() > 0) { if(added == 0 and graph.size() > 0) {
logger->error("Circular dependency detected! IPs not available:"); logger->error("Circular dependency detected! IPs not available:");
for(auto& [key, value] : graph) { for(auto& [key, value] : graph) {
(void) value;
logger->error(" {}", key); logger->error(" {}", key);
} }
break; break;
......
...@@ -242,6 +242,8 @@ public: ...@@ -242,6 +242,8 @@ public:
{ {
logger->info("Vertices:"); logger->info("Vertices:");
for(auto& [vertexId, vertex] : vertices) { for(auto& [vertexId, vertex] : vertices) {
(void) vertexId;
// format connected vertices into a list // format connected vertices into a list
std::stringstream ssEdges; std::stringstream ssEdges;
for(auto& edge : vertex->edges) { for(auto& edge : vertex->edges) {
...@@ -253,6 +255,8 @@ public: ...@@ -253,6 +255,8 @@ public:
logger->info("Edges:"); logger->info("Edges:");
for(auto& [edgeId, edge] : edges) { for(auto& [edgeId, edge] : edges) {
(void) edgeId;
logger->info(" {}: {} -> {}", *edge, edge->from, edge->to); logger->info(" {}: {} -> {}", *edge, edge->from, edge->to);
} }
} }
......
...@@ -48,8 +48,10 @@ ...@@ -48,8 +48,10 @@
#define PCI_FILTER_DEFAULT_FPGA { \ #define PCI_FILTER_DEFAULT_FPGA { \
.id = { \ .id = { \
.vendor = FPGA_PCI_VID_XILINX, \ .vendor = FPGA_PCI_VID_XILINX, \
.device = FPGA_PCI_PID_VFPGA \ .device = FPGA_PCI_PID_VFPGA, \
} \ .class_code = 0 \
}, \
.slot = { } \
} }
namespace villas { namespace villas {
......
...@@ -161,7 +161,7 @@ private: ...@@ -161,7 +161,7 @@ private:
virtual IpCore* create() = 0; virtual IpCore* create() = 0;
/// Configure IP instance from JSON config /// Configure IP instance from JSON config
virtual bool configureJson(IpCore& ip, json_t *json) virtual bool configureJson(IpCore& /* ip */, json_t* /* json */)
{ return true; } { return true; }
......
...@@ -45,6 +45,8 @@ find_package(Threads) ...@@ -45,6 +45,8 @@ find_package(Threads)
add_library(villas-fpga SHARED ${SOURCES}) add_library(villas-fpga SHARED ${SOURCES})
set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -Wextra")
target_compile_definitions(villas-fpga PRIVATE target_compile_definitions(villas-fpga PRIVATE
BUILDID=\"abc\" BUILDID=\"abc\"
_GNU_SOURCE _GNU_SOURCE
......
...@@ -67,7 +67,7 @@ bool Fifo::init() ...@@ -67,7 +67,7 @@ bool Fifo::init()
fifo_cfg.Axi4BaseAddress = getAddrMapped(this->baseaddr_axi4); fifo_cfg.Axi4BaseAddress = getAddrMapped(this->baseaddr_axi4);
// use AXI4 for Data, AXI4-Lite for control // use AXI4 for Data, AXI4-Lite for control
fifo_cfg.Datainterface = (this->baseaddr_axi4 != -1) ? 1 : 0; fifo_cfg.Datainterface = (this->baseaddr_axi4 != static_cast<size_t>(-1)) ? 1 : 0;
if (XLlFifo_CfgInitialize(&xFifo, &fifo_cfg, getBaseaddr()) != XST_SUCCESS) if (XLlFifo_CfgInitialize(&xFifo, &fifo_cfg, getBaseaddr()) != XST_SUCCESS)
return false; return false;
......
...@@ -53,7 +53,7 @@ AxiStreamSwitch::init() ...@@ -53,7 +53,7 @@ AxiStreamSwitch::init()
XAxisScr_RegUpdateEnable(&xSwitch); XAxisScr_RegUpdateEnable(&xSwitch);
// initialize internal mapping // initialize internal mapping
for(int portMaster = 0; portMaster < portsMaster.size(); portMaster++) { for(size_t portMaster = 0; portMaster < portsMaster.size(); portMaster++) {
portMapping[portMaster] = PORT_DISABLED; portMapping[portMaster] = PORT_DISABLED;
} }
......
...@@ -19,14 +19,16 @@ struct criterion_prefix_data { ...@@ -19,14 +19,16 @@ struct criterion_prefix_data {
const char *color; const char *color;
}; };
static void format_msg(char *buf, size_t buflen, const char *msg, va_list args) static int format_msg(char *buf, size_t buflen, const char *msg, va_list args)
{ {
int len = vsnprintf(buf, buflen, msg, args); int len = vsnprintf(buf, buflen, msg, args);
/* Strip new line */ /* Strip new line */
char *nl = strchr(buf, '\n'); char *nl = strchr(buf, '\n');
if (nl) if (nl)
*nl = 0; *nl = 0;
return len;
} }
void criterion_log_noformat(enum criterion_severity severity, const char *msg) void criterion_log_noformat(enum criterion_severity severity, const char *msg)
......
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