dma.hpp 3.28 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
/** DMA driver
 *
 * @author Daniel Krebs <github@daniel-krebs.net>
 * @copyright 2018, RWTH Institute for Automation of Complex Power Systems (ACS)
 * @license GNU General Public License (version 3)
 *
 * VILLASfpga
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 ******************************************************************************/

/** @addtogroup fpga VILLASfpga
 * @{
 */

#pragma once

#include <xilinx/xaxidma.h>

31 32
#include <villas/memory.hpp>
#include <villas/fpga/ip_node.hpp>
33 34 35 36 37 38 39 40 41 42 43 44 45

namespace villas {
namespace fpga {
namespace ip {

class Dma : public IpNode
{
public:
	friend class DmaFactory;

	bool init();
	bool reset();

Daniel Krebs's avatar
Daniel Krebs committed
46
	// memory-mapped to stream (MM2S)
47
	bool write(const MemoryBlock& mem, size_t len);
Daniel Krebs's avatar
Daniel Krebs committed
48 49

	// stream to memory-mapped (S2MM)
50
	bool read(const MemoryBlock& mem, size_t len);
51

52
	size_t writeComplete()
53 54
	{ return hasScatterGather() ? writeCompleteSG() : writeCompleteSimple(); }

55
	size_t readComplete()
56 57
	{ return hasScatterGather() ? readCompleteSG() : readCompleteSimple(); }

58
	bool memcpy(const MemoryBlock& src, const MemoryBlock& dst, size_t len);
59

60 61
	bool makeAccesibleFromVA(const MemoryBlock& mem);

62 63 64 65
	inline bool
	hasScatterGather() const
	{ return hasSG; }

66 67 68 69 70 71 72 73
	const StreamVertex&
	getDefaultSlavePort() const
	{ return getSlavePort(s2mmPort); }

	const StreamVertex&
	getDefaultMasterPort() const
	{ return getMasterPort(mm2sPort); }

74
private:
75 76 77 78
	bool writeSG(const void* buf, size_t len);
	bool readSG(void* buf, size_t len);
	size_t writeCompleteSG();
	size_t readCompleteSG();
79

80 81 82 83
	bool writeSimple(const void* buf, size_t len);
	bool readSimple(void* buf, size_t len);
	size_t writeCompleteSimple();
	size_t readCompleteSimple();
84

85 86 87 88
public:
	static constexpr const char* s2mmPort = "S2MM";
	static constexpr const char* mm2sPort = "MM2S";

89 90
	bool isMemoryBlockAccesible(const MemoryBlock& mem, const std::string& interface);

91 92 93 94 95 96 97 98 99 100 101 102
private:
	static constexpr char registerMemory[] = "Reg";

	static constexpr char mm2sInterrupt[] = "mm2s_introut";
	static constexpr char mm2sInterface[] = "M_AXI_MM2S";

	static constexpr char s2mmInterrupt[] = "s2mm_introut";
	static constexpr char s2mmInterface[] = "M_AXI_S2MM";

	// optional Scatter-Gather interface to access descriptors
	static constexpr char sgInterface[] = "M_AXI_SG";

103
	std::list<MemoryBlockName> getMemoryBlocks() const
104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135
	{ return { registerMemory }; }

	XAxiDma xDma;
	bool hasSG;
};



class DmaFactory : public IpNodeFactory {
public:
	DmaFactory();

	IpCore* create()
	{ return new Dma; }

	std::string
	getName() const
	{ return "Dma"; }

	std::string
	getDescription() const
	{ return "Xilinx's AXI4 Direct Memory Access Controller"; }

	Vlnv getCompatibleVlnv() const
	{ return {"xilinx.com:ip:axi_dma:"}; }
};

} // namespace ip
} // namespace fpga
} // namespace villas

/** @} */