Programming languages used in this repository

  •   VHDL
    84.71 %
  •   Verilog
    15.1 %
  •   Coq
    0.12 %
  •   SystemVerilog
    0.04 %
  •   Tcl
    0.02 %

Commit statistics for master Jun 25 - Jun 25

  • Total: 2 commits
  • Average per day: 2.0 commits
  • Authors: 2

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