Commit f4fbc78b authored by Markus Mirz's avatar Markus Mirz
Browse files

restructure circuit examples

parent 72b7fc1e
......@@ -9,39 +9,18 @@ endif()
# targets
set(CIRCUIT_SOURCES
# Dynamic phasor examples
Circuits/DP_VS_R1.cpp
Circuits/DP_CS_R1.cpp
Circuits/DP_VS_RL1.cpp
Circuits/DP_VS_RL2.cpp
Circuits/DP_VS_RC1.cpp
Circuits/DP_CS_R2CL.cpp
Circuits/DP_VS_CS_R4.cpp
Circuits/DP_VS_R2L3.cpp
DP_Basics/DP_VS_RL_f60.cpp
DP_Basics/DP_VS_RL_f60_largeTs.cpp
DP_Basics/DP_VS_RL_f60_vlargeTs.cpp
DP_Basics/DP_VS_RL_f500.cpp
DP_Basics/DP_VS_RL_f500_largeTs.cpp
DP_Basics/DP_VS_RL_f500_ph500.cpp
Circuits/DP_Circuits.cpp
Circuits/DP_Basics_DP_Sims.cpp
#Circuits/DP_VS_PiLine_R.cpp
#Circuits/DP_VS_Trafo_R.cpp
#Circuits/DP_ResVS_RL_Switch.cpp
# EMT examples
Circuits/EMT_VS_R1.cpp
Circuits/EMT_VS_RC1.cpp
Circuits/EMT_CS_R1.cpp
# EMT examples
Circuits/EMT_VS_RL1.cpp
Circuits/EMT_CS_R2CL.cpp
Circuits/EMT_VS_R2L3.cpp
Circuits/EMT_VS_CS_R4_AC.cpp
Circuits/EMT_VS_CS_R4_DC.cpp
DP_Basics/EMT_VS_RL_f60.cpp
DP_Basics/EMT_VS_RL_f60_largeTs.cpp
DP_Basics/EMT_VS_RL_f500.cpp
Circuits/EMT_Circuits.cpp
Circuits/DP_Basics_EMT_Sims.cpp
#Circuits/EMT_ResVS_RL_Switch.cpp
......@@ -76,8 +55,8 @@ endif()
if(WITH_RT)
set(RT_SOURCES
RealTime/RT_DP_CS_R_1.cpp
RealTime/RT_DP_ResVS_RL1.cpp
RealTime/RT_DP_CS_R1.cpp
RealTime/RT_DP_VS_RL2.cpp
)
endif()
......
/** Reference Circuits
*
* @author Markus Mirz <mmirz@eonerc.rwth-aachen.de>
* @copyright 2017-2018, Institute for Automation of Complex Power Systems, EONERC
*
* DPsim
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*********************************************************************************/
#include <DPsim.h>
using namespace DPsim;
using namespace CPS::DP;
using namespace CPS::DP::Ph1;
void DP_VS_RL_f60_largeTs();
void DP_VS_RL_f60_vlargeTs();
void DP_VS_RL_f60();
void DP_VS_RL_f500_largeTs();
void DP_VS_RL_f500_ph500();
void DP_VS_RL_f500();
int main(int argc, char* argv[]) {
DP_VS_RL_f60_largeTs();
DP_VS_RL_f60_vlargeTs();
DP_VS_RL_f60();
DP_VS_RL_f500_largeTs();
DP_VS_RL_f500_ph500();
DP_VS_RL_f500();
}
void DP_VS_RL_f60_largeTs() {
Real timeStep = 0.01;
Real finalTime = 0.2;
String simName = "DP_VS_RL_f60_largeTs";
Logger::setLogDir("logs/"+simName);
// Nodes
auto n1 = Node::make("n1");
auto n2 = Node::make("n2");
auto n3 = Node::make("n3");
// Components
auto vs = VoltageSource::make("vs");
vs->setParameters(Complex(230, 0), 10);
auto rline = Resistor::make("r_line");
rline->setParameters(1);
auto lline = Inductor::make("l_line");
lline->setParameters(0.02);
auto rload = Resistor::make("r_load");
rload->setParameters(10);
// Connections
vs->connect({ Node::GND, n1 });
rline->connect({ n1, n2 });
lline->connect({ n2, n3 });
rload->connect({ n3, Node::GND });
// Define system topology
auto sys = SystemTopology(50,
SystemNodeList{n1, n2, n3},
SystemComponentList{vs, rline, lline, rload});
// Logger
auto logger = DataLogger::make(simName);
logger->addAttribute("v1", n1->attributeMatrixComp("v"));
logger->addAttribute("v2", n2->attributeMatrixComp("v"));
logger->addAttribute("v3", n3->attributeMatrixComp("v"));
logger->addAttribute("i_line", rline->attributeMatrixComp("i_intf"));
Simulation sim(simName, Logger::Level::info);
sim.setSystem(sys);
sim.setTimeStep(timeStep);
sim.setFinalTime(finalTime);
sim.initialize();
sim.addLogger(logger);
sim.run();
}
void DP_VS_RL_f60_vlargeTs() {
Real timeStep = 0.05;
Real finalTime = 0.2;
String simName = "DP_VS_RL_f60_vlargeTs";
Logger::setLogDir("logs/"+simName);
// Nodes
auto n1 = Node::make("n1");
auto n2 = Node::make("n2");
auto n3 = Node::make("n3");
// Components
auto vs = VoltageSource::make("vs");
vs->setParameters(Complex(230, 0), 10);
auto rline = Resistor::make("r_line");
rline->setParameters(1);
auto lline = Inductor::make("l_line");
lline->setParameters(0.02);
auto rload = Resistor::make("r_load");
rload->setParameters(10);
// Connections
vs->connect({ Node::GND, n1 });
rline->connect({ n1, n2 });
lline->connect({ n2, n3 });
rload->connect({ n3, Node::GND });
// Define system topology
auto sys = SystemTopology(50,
SystemNodeList{n1, n2, n3},
SystemComponentList{vs, rline, lline, rload});
// Logger
auto logger = DataLogger::make(simName);
logger->addAttribute("v1", n1->attributeMatrixComp("v"));
logger->addAttribute("v2", n2->attributeMatrixComp("v"));
logger->addAttribute("v3", n3->attributeMatrixComp("v"));
logger->addAttribute("i_line", rline->attributeMatrixComp("i_intf"));
Simulation sim(simName, Logger::Level::info);
sim.setSystem(sys);
sim.setTimeStep(timeStep);
sim.setFinalTime(finalTime);
sim.initialize();
sim.addLogger(logger);
sim.run();
}
void DP_VS_RL_f60() {
Real timeStep = 0.0001;
Real finalTime = 0.2;
String simName = "DP_VS_RL_f60";
Logger::setLogDir("logs/"+simName);
// Nodes
auto n1 = Node::make("n1");
auto n2 = Node::make("n2");
auto n3 = Node::make("n3");
// Components
auto vs = VoltageSource::make("vs");
vs->setParameters(Complex(230, 0), 10);
auto rline = Resistor::make("r_line");
rline->setParameters(1);
auto lline = Inductor::make("l_line");
lline->setParameters(0.02);
auto rload = Resistor::make("r_load");
rload->setParameters(10);
// Connections
vs->connect({ Node::GND, n1 });
rline->connect({ n1, n2 });
lline->connect({ n2, n3 });
rload->connect({ n3, Node::GND });
// Define system topology
auto sys = SystemTopology(50,
SystemNodeList{n1, n2, n3},
SystemComponentList{vs, rline, lline, rload});
// Logger
auto logger = DataLogger::make(simName);
logger->addAttribute("v1", n1->attributeMatrixComp("v"));
logger->addAttribute("v2", n2->attributeMatrixComp("v"));
logger->addAttribute("v3", n3->attributeMatrixComp("v"));
logger->addAttribute("i_line", rline->attributeMatrixComp("i_intf"));
Simulation sim(simName, Logger::Level::info);
sim.setSystem(sys);
sim.setTimeStep(timeStep);
sim.setFinalTime(finalTime);
sim.initialize();
sim.addLogger(logger);
sim.run();
}
void DP_VS_RL_f500_largeTs() {
Real timeStep = 0.002;
Real finalTime = 0.2;
String simName = "DP_VS_RL_f500_largeTs";
Logger::setLogDir("logs/"+simName);
// Nodes
auto n1 = Node::make("n1");
auto n2 = Node::make("n2");
auto n3 = Node::make("n3");
// Components
auto vs = VoltageSource::make("vs");
vs->setParameters(Complex(230, 0), 450);
auto rline = Resistor::make("r_line");
rline->setParameters(1);
auto lline = Inductor::make("l_line");
lline->setParameters(0.02);
auto rload = Resistor::make("r_load");
rload->setParameters(10);
// Connections
vs->connect({ Node::GND, n1 });
rline->connect({ n1, n2 });
lline->connect({ n2, n3 });
rload->connect({ n3, Node::GND });
// Define system topology
auto sys = SystemTopology(50,
SystemNodeList{n1, n2, n3},
SystemComponentList{vs, rline, lline, rload});
// Logger
auto logger = DataLogger::make(simName);
logger->addAttribute("v1", n1->attributeMatrixComp("v"));
logger->addAttribute("v2", n2->attributeMatrixComp("v"));
logger->addAttribute("v3", n3->attributeMatrixComp("v"));
logger->addAttribute("i_line", rline->attributeMatrixComp("i_intf"));
Simulation sim(simName, Logger::Level::info);
sim.setSystem(sys);
sim.setTimeStep(timeStep);
sim.setFinalTime(finalTime);
sim.initialize();
sim.addLogger(logger);
sim.run();
}
void DP_VS_RL_f500_ph500() {
Real timeStep = 0.002;
Real finalTime = 0.2;
String simName = "DP_VS_RL_f500_ph500";
Logger::setLogDir("logs/"+simName);
// Nodes
auto n1 = Node::make("n1");
auto n2 = Node::make("n2");
auto n3 = Node::make("n3");
// Components
auto vs = VoltageSource::make("vs");
vs->setParameters(Complex(230, 0));
auto rline = Resistor::make("r_line");
rline->setParameters(1);
auto lline = Inductor::make("l_line");
lline->setParameters(0.02);
auto rload = Resistor::make("r_load");
rload->setParameters(10);
// Connections
vs->connect({ Node::GND, n1 });
rline->connect({ n1, n2 });
lline->connect({ n2, n3 });
rload->connect({ n3, Node::GND });
// Define system topology
auto sys = SystemTopology(500,
SystemNodeList{n1, n2, n3},
SystemComponentList{vs, rline, lline, rload});
// Logger
auto logger = DataLogger::make(simName);
logger->addAttribute("v1", n1->attributeMatrixComp("v"));
logger->addAttribute("v2", n2->attributeMatrixComp("v"));
logger->addAttribute("v3", n3->attributeMatrixComp("v"));
logger->addAttribute("i_line", rline->attributeMatrixComp("i_intf"));
Simulation sim(simName, Logger::Level::info);
sim.setSystem(sys);
sim.setTimeStep(timeStep);
sim.setFinalTime(finalTime);
sim.initialize();
sim.addLogger(logger);
sim.run();
}
void DP_VS_RL_f500() {
Real timeStep = 0.00001;
Real finalTime = 0.2;
String simName = "DP_VS_RL_f500";
Logger::setLogDir("logs/"+simName);
// Nodes
auto n1 = Node::make("n1");
auto n2 = Node::make("n2");
auto n3 = Node::make("n3");
// Components
auto vs = VoltageSource::make("vs");
vs->setParameters(Complex(230, 0), 450);
auto rline = Resistor::make("r_line");
rline->setParameters(1);
auto lline = Inductor::make("l_line");
lline->setParameters(0.02);
auto rload = Resistor::make("r_load");
rload->setParameters(10);
// Connections
vs->connect({ Node::GND, n1 });
rline->connect({ n1, n2 });
lline->connect({ n2, n3 });
rload->connect({ n3, Node::GND });
// Define system topology
auto sys = SystemTopology(50,
SystemNodeList{n1, n2, n3},
SystemComponentList{vs, rline, lline, rload});
// Logger
auto logger = DataLogger::make(simName);
logger->addAttribute("v1", n1->attributeMatrixComp("v"));
logger->addAttribute("v2", n2->attributeMatrixComp("v"));
logger->addAttribute("v3", n3->attributeMatrixComp("v"));
logger->addAttribute("i_line", rline->attributeMatrixComp("i_intf"));
Simulation sim(simName, Logger::Level::info);
sim.setSystem(sys);
sim.setTimeStep(timeStep);
sim.setFinalTime(finalTime);
sim.initialize();
sim.addLogger(logger);
sim.run();
}
......@@ -25,8 +25,17 @@ using namespace DPsim;
using namespace CPS::EMT;
using namespace CPS::EMT::Ph1;
void EMT_VS_RL_f60_largeTs();
void EMT_VS_RL_f60();
void EMT_VS_RL_f500();
int main(int argc, char* argv[]) {
// Define simulation scenario
EMT_VS_RL_f60_largeTs();
EMT_VS_RL_f60();
EMT_VS_RL_f500();
}
void EMT_VS_RL_f60_largeTs() {
Real timeStep = 0.01;
Real finalTime = 0.2;
String simName = "EMT_VS_RL_f60_largeTs";
......@@ -75,6 +84,108 @@ int main(int argc, char* argv[]) {
sim.addLogger(logger);
sim.run();
}
void EMT_VS_RL_f60() {
Real timeStep = 0.0001;
Real finalTime = 0.2;
String simName = "EMT_VS_RL_f60";
Logger::setLogDir("logs/"+simName);
// Nodes
auto n1 = Node::make("n1");
auto n2 = Node::make("n2");
auto n3 = Node::make("n3");
// Components
auto vs = VoltageSource::make("vs");
vs->setParameters(Complex(230, 0), 60);
auto rline = Resistor::make("r_line");
rline->setParameters(1);
auto lline = Inductor::make("l_line");
lline->setParameters(0.02);
auto rload = Resistor::make("r_load");
rload->setParameters(10);
// Connections
vs->connect({ Node::GND, n1 });
rline->connect({ n1, n2 });
lline->connect({ n2, n3 });
rload->connect({ n3, Node::GND });
return 0;
// Define system topology
auto sys = SystemTopology(50,
SystemNodeList{n1, n2, n3},
SystemComponentList{vs, rline, lline, rload});
// Logger
auto logger = DataLogger::make(simName);
logger->addAttribute("v1", n1->attributeMatrixReal("v"));
logger->addAttribute("v2", n2->attributeMatrixReal("v"));
logger->addAttribute("v3", n3->attributeMatrixReal("v"));
logger->addAttribute("i_line", rline->attributeMatrixReal("i_intf"));
Simulation sim(simName, Logger::Level::info);
sim.setSystem(sys);
sim.setTimeStep(timeStep);
sim.setFinalTime(finalTime);
sim.setDomain(Domain::EMT);
sim.initialize();
sim.addLogger(logger);
sim.run();
}
void EMT_VS_RL_f500() {
Real timeStep = 0.00001;
Real finalTime = 0.2;
String simName = "EMT_VS_RL_f500";
Logger::setLogDir("logs/"+simName);
// Nodes
auto n1 = Node::make("n1");
auto n2 = Node::make("n2");
auto n3 = Node::make("n3");
// Components
auto vs = VoltageSource::make("vs");
vs->setParameters(Complex(230, 0), 500);
auto rline = Resistor::make("r_line");
rline->setParameters(1);
auto lline = Inductor::make("l_line");
lline->setParameters(0.02);
auto rload = Resistor::make("r_load");
rload->setParameters(10);
// Connections
vs->connect({ Node::GND, n1 });
rline->connect({ n1, n2 });
lline->connect({ n2, n3 });
rload->connect({ n3, Node::GND });
// Define system topology
auto sys = SystemTopology(50,
SystemNodeList{n1, n2, n3},
SystemComponentList{vs, rline, lline, rload});
// Logger
auto logger = DataLogger::make(simName);
logger->addAttribute("v1", n1->attributeMatrixReal("v"));
logger->addAttribute("v2", n2->attributeMatrixReal("v"));
logger->addAttribute("v3", n3->attributeMatrixReal("v"));
logger->addAttribute("i_line", rline->attributeMatrixReal("i_intf"));
Simulation sim(simName, Logger::Level::info);
sim.setSystem(sys);
sim.setTimeStep(timeStep);
sim.setFinalTime(finalTime);
sim.setDomain(Domain::EMT);
sim.initialize();
sim.addLogger(logger);
sim.run();
}
/** Reference Circuits
*
* @author Markus Mirz <mmirz@eonerc.rwth-aachen.de>
* @copyright 2017-2018, Institute for Automation of Complex Power Systems, EONERC
*
* DPsim
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*********************************************************************************/
#include <DPsim.h>
using namespace DPsim;
using namespace CPS::DP;
using namespace CPS::DP::Ph1;
int main(int argc, char* argv[]) {
// Define simulation scenario
Real timeStep = 0.0001;
Real finalTime = 0.1;
String simName = "DP_CS_R1";
Logger::setLogDir("logs/"+simName);
// Nodes
auto n1 = Node::make("n1");
// Components
auto cs = CurrentSource::make("cs");
auto r1 = Resistor::make("r_1");
// Topology
cs->connect({ Node::GND, n1 });
r1->connect({ Node::GND, n1 });
cs->setParameters(Complex(10, 0));
r1->setParameters(1);
// Define system topology
auto sys = SystemTopology(50, SystemNodeList{n1}, SystemComponentList{cs, r1});
// Logging
auto logger = DataLogger::make(simName);
logger->addAttribute("v1", n1->attribute("v"));
logger->addAttribute("i10", r1->attribute("i_intf"));
Simulation sim(simName, sys, timeStep, finalTime, Domain::DP, Solver::Type::MNA, Logger::Level::debug);
sim.addLogger(logger);
sim.run();
return 0;
}