Commit e7a9e16c authored by Markus Mirz's avatar Markus Mirz
Browse files

fixing test examples

parent 9afe35a5
......@@ -28,7 +28,7 @@ int main(int argc, char* argv[]) {
Real timeStep = 0.00005;
Real omega = 2.0*M_PI*50.0;
Real finalTime = 0.2;
String simName = "DP_IdealVS1_R_2";
String simName = "DP_IdealVS_R_2";
Component::List comps = {
VoltageSource::make("v_in", 0, 1, Complex(10, 0)),
......
......@@ -6,11 +6,11 @@ import subprocess
PATH = os.path.dirname(__file__)
def test_IdealVS_R_1_cpp():
name = 'DP_IdealVS_R_1'
name = 'IdealVS_R_2'
frequency = 50
subprocess.run(PATH + "/../../../build/Examples/Cxx/" + name, shell=True, check=True)
results = rt.read_timeseries_dpsim_cmpl('Logs/' + name + '_LeftVector.csv')
expected = rt.read_timeseries_simulink(PATH + '/../../Results/Simulink/Circuits/SL_' + name + '.csv')
subprocess.run(PATH + "/../../../build/Examples/Cxx/DP_" + name, shell=True, check=True)
results = rt.read_timeseries_dpsim_cmpl('Logs/DP_' + name + '_LeftVector.csv')
expected = rt.read_timeseries_dpsim_real(PATH + '/../../Results/Simulink/Circuits/SL_' + name + '.csv')
err = 0
err += ts.TimeSeries.rmse(expected[0], results[0].dynphasor_shift_to_emt('n1_emt', frequency))
......
......@@ -7,20 +7,21 @@ import dataprocessing.timeseries as ts
PATH = os.path.dirname(__file__)
def test_IdealVS_R1():
sim = dpsim.Simulation('IdealVS_R1',
sim = dpsim.Simulation('IdealVS_R_2',
[
dp.VoltageSource("v_in", 1, 0, 10),
dp.VoltageSource("v_in", 0, 1, 10),
dp.Resistor("r_1", 0, -1, 1),
dp.Resistor("r_2", 1, -1, 1),
dp.Resistor("r_3", 1, -1, 1)
],
duration=0.3
duration=0.2,
timestep=0.00005
)
sim.run()
results = rt.read_timeseries_dpsim_cmpl('Logs/' + sim.name() + '_LeftVector.csv')
expected = rt.read_timeseries_dpsim_real(PATH + '/../../Results/Simulink/Circuits/SL_' + sim.name() + '.csv')
expected = rt.read_timeseries_dpsim_real('Examples/Results/Simulink/Circuits/SL_' + sim.name() + '.csv')
err = 0
err += ts.TimeSeries.rmse(expected[0], results[0].dynphasor_shift_to_emt('n1_emt', 50))
......@@ -28,4 +29,4 @@ def test_IdealVS_R1():
print("Total RMSE: %g" % (err))
assert err < 1e-6
assert err < 1e-4
Subproject commit 4524229e02fff1b4fe58349190141bc45948ef19
Subproject commit 41f96a49cbfe119ac4a6a8f31a82e1f07a3c6581
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