Commit c2251229 authored by Markus Mirz's avatar Markus Mirz
Browse files

Merge branch 'development' of git.rwth-aachen.de:acs/core/simulation/dpsim into development

parents c0eb8357 0ff9b317
......@@ -51,7 +51,7 @@ int main(int argc, char *argv[]) {
ecs->connect({ Node::GND, n1 });
r1->connect({ Node::GND, n1 });
intf.addImport(ecs->attribute<Complex>("i_ref"), 0);
intf.addImport(ecs->attribute<Complex>("I_ref"), 0);
intf.addExport(ecs->attribute<Complex>("v_comp"), 0);
auto sys = SystemTopology(50, SystemNodeList{n1}, SystemComponentList{ecs, r1});
......
......@@ -76,7 +76,7 @@ int main(int argc, char *argv[]) {
vs1->connect({ Node::GND, n1 });
r01->connect({ n1, n2 });
intf.addImport(evs->attribute<Complex>("v_ref"), 0);
intf.addImport(evs->attribute<Complex>("V_ref"), 0);
intf.addExport(evs->attribute<Complex>("i_comp"), 0);
auto sys = SystemTopology(50, SystemNodeList{n1, n2}, SystemComponentList{evs, vs1, r01});
......@@ -99,7 +99,7 @@ int main(int argc, char *argv[]) {
//auto ecs_switch = CurrentSource::make("i_switch", GND, 1, Complex(0, 0));
//auto r01 = Resistor::make("r_0_1", 0, 1, 1);
intf.addImport(ecs->attribute<Complex>("i_ref"), 0);
intf.addImport(ecs->attribute<Complex>("I_ref"), 0);
intf.addExport(ecs->attribute<Complex>("v_comp"), 0);
//intf.addImport(ecs_switch->attribute('CurrentRef'), 1);
......
......@@ -80,7 +80,7 @@ int main(int argc, char *argv[])
comps = SystemComponentList{evs, vs, l1, r1};
nodes = SystemNodeList{Node::GND, n1, n2, n3};
intf.addImport(evs->attribute<Complex>("v_ref"), 0);
intf.addImport(evs->attribute<Complex>("V_ref"), 0);
intf.addExport(evs->attribute<Complex>("i_comp"), 0);
}
else if (String(argv[1]) == "1") {
......@@ -109,7 +109,7 @@ int main(int argc, char *argv[])
comps = SystemComponentList{ecs, sw, r2A, r2B};
nodes = SystemNodeList{Node::GND, n4, n5};
intf.addImport(ecs->attribute<Complex>("i_ref"), 0);
intf.addImport(ecs->attribute<Complex>("I_ref"), 0);
intf.addExport(ecs->attribute<Complex>("v_comp"), 0);
}
else {
......
......@@ -60,7 +60,7 @@ int main(int argc, char* argv[])
auto sys = SystemTopology(50, SystemNodeList{Node::GND, n1, n2, n3, n4}, SystemComponentList{evs, rs, rl, ll, rL});
auto intf = Interface("/villas1-in", "/villas1-out");
intf.addImport(evs->attribute<Complex>("v_ref"), 0);
intf.addImport(evs->attribute<Complex>("V_ref"), 0);
intf.addExport(evs->attribute<Complex>("i_comp"), 0);
Real timeStep = 0.001;
......
......@@ -64,7 +64,7 @@ int main(int argc, char* argv[])
auto intf = Interface("/villas1-in", "/villas1-out", &conf);
intf.addImport(evs->attribute<Complex>("v_ref"), 0);
intf.addImport(evs->attribute<Complex>("V_ref"), 0);
intf.addExport(evs->attribute<Complex>("i_comp"), 0);
Real timeStep = 0.001;
......
......@@ -93,7 +93,7 @@ int main(int argc, char *argv[]) {
sys.mComponents.push_back(filtP_profile);
// Register interface current source and voltage drop
intf1.addImport(ecs->attribute<Complex>("i_ref"), 0);
intf1.addImport(ecs->attribute<Complex>("I_ref"), 0);
intf1.addExport(ecs->attribute<Complex>("v_comp"), 0);
// TODO: gain by 20e8
......@@ -166,7 +166,7 @@ int main(int argc, char *argv[]) {
// Register voltage source reference and current flowing through source
// multiply with -1 to consider passive sign convention
intf1.addImport(evs->attribute<Complex>("v_ref"), 0);
intf1.addImport(evs->attribute<Complex>("V_ref"), 0);
// TODO: invalid sign
intf1.addExport(evs->attribute<Complex>("i_comp"), 0);
......
......@@ -6,45 +6,45 @@ class Left(threading.Thread):
def run(self):
# Nodes
gnd = dpsim.dp.Node.GND()
n1 = dpsim.dp.Node("n1")
n2 = dpsim.dp.Node("n2")
n1 = dpsim.dp.Node('n1')
n2 = dpsim.dp.Node('n2')
vs = dpsim.dp.ph1.VoltageSourceNorton("v_s", [n1, gnd], 10000+0j, 1)
evs = dpsim.dp.ph1.VoltageSource("v_ext", [n2, gnd], 0+0j)
l1 = dpsim.dp.ph1.Inductor("l_1", [n1, n2], 1e-3)
vs = dpsim.dp.ph1.VoltageSourceNorton('v_s', [n1, gnd], 10000+0j, 1)
evs = dpsim.dp.ph1.VoltageSource('v_ext', [n2, gnd], 0+0j)
l1 = dpsim.dp.ph1.Inductor('l_1', [n1, n2], 1e-3)
intf = dpsim.open_interface("/dpsim12", "/dpsim21", samplelen = 2)
intf.import_attribute(evs, "v_ref", 1, 0, 1)
intf.export_attribute(evs, "i_comp", 1, 0, 1)
intf = dpsim.open_interface('/dpsim12', '/dpsim21', samplelen = 2)
intf.import_attribute(evs, 'V_ref', 1, 0, 1)
intf.export_attribute(evs, 'i_comp', 1, 0, 1)
sys = dpsim.SystemTopology(50, [gnd, n1, n2], [evs, vs, l1])
sim = dpsim.Simulation("shmem1", sys, duration = 1)
sim = dpsim.Simulation('shmem1', sys, duration = 1)
sim.add_interface(intf)
print("Starting simulation on left side")
print('Starting simulation on left side')
sim.run()
class Right(threading.Thread):
def run(self):
# Nodes
gnd = dpsim.dp.Node.GND()
n3 = dpsim.dp.Node("n3")
n3 = dpsim.dp.Node('n3')
# Components
ecs = dpsim.dp.ph1.CurrentSource("i_ext", [n3, gnd], 0+0j)
r1 = dpsim.dp.ph1.Resistor("r_1", [n3, gnd], 1)
ecs = dpsim.dp.ph1.CurrentSource('i_ext', [n3, gnd], 0+0j)
r1 = dpsim.dp.ph1.Resistor('r_1', [n3, gnd], 1)
intf = dpsim.open_interface("/dpsim21", "/dpsim12", samplelen = 2)
intf.import_attribute(ecs, "i_ref", 1, 0, 1)
intf.export_attribute(r1, "v_comp", 1, 0, 1)
intf = dpsim.open_interface('/dpsim21', '/dpsim12', samplelen = 2)
intf.import_attribute(ecs, 'I_ref', 1, 0, 1)
intf.export_attribute(r1, 'v_comp', 1, 0, 1)
sys = dpsim.SystemTopology(50, [gnd, n3], [ecs, r1])
sim = dpsim.Simulation("shmem2", sys, duration = 1)
sim = dpsim.Simulation('shmem2', sys, duration = 1)
sim.add_interface(intf)
print("Starting simulation on right side")
print('Starting simulation on right side')
sim.run()
def test_ShmemDistributedDirect():
......
......@@ -9,7 +9,7 @@ from dpsim.Event import Event
def my_callback(event, sim, myvar):
assert myvar == 1337
print("Received Event: %s" % event)
print('Received Event: %s' % event)
if event in [ Event.done, Event.stopped, Event.stopped, Event.failed, Event.overrun ]:
el = asyncio.get_event_loop()
......@@ -20,11 +20,11 @@ def test_async():
# Nodes
gnd = dpsim.dp.Node.GND()
n1 = dpsim.dp.Node("n1")
n1 = dpsim.dp.Node('n1')
# Components
v1 = dpsim.dp.ph1.VoltageSource("v_1", [gnd, n1], v_ref=10)
r1 = dpsim.dp.ph1.Resistor("r_1", [n1, gnd], resistance=1)
v1 = dpsim.dp.ph1.VoltageSource('v_1', [gnd, n1], V_ref=10)
r1 = dpsim.dp.ph1.Resistor('r_1', [n1, gnd], R=1)
system = dpsim.SystemTopology(50, [gnd, n1], [v1, r1])
......@@ -46,5 +46,5 @@ def test_async():
el.run_forever()
if __name__ == "__main__":
if __name__ == '__main__':
test_async()
......@@ -3,23 +3,23 @@ import pytest
def test_read():
gnd = dpsim.dp.Node.GND()
c = dpsim.dp.ph1.Capacitor('c1', [gnd, gnd], capacitance=1.234);
c = dpsim.dp.ph1.Capacitor('c1', [gnd, gnd], C=1.234);
assert c.capacitance == 1.234
assert c.C == 1.234
assert c.name == 'c1'
def test_write():
gnd = dpsim.dp.Node.GND()
c = dpsim.dp.ph1.Capacitor('c1', [gnd, gnd], capacitance=1.234);
c = dpsim.dp.ph1.Capacitor('c1', [gnd, gnd], C=1.234);
c.capacitance = 5
c.C = 5
assert c.capacitance == 5
assert c.C == 5
def test_invalid():
with pytest.raises(AttributeError) as e_info:
gnd = dpsim.dp.Node.GND()
c = dpsim.dp.ph1.Capacitor('c1', [gnd, gnd], capacitance=1.234);
c = dpsim.dp.ph1.Capacitor('c1', [gnd, gnd], C=1.234);
# dp.Capacitor does not have an attribute named 'doesnotexist'
# Accessing it should throw a AttributeError exception!
......@@ -28,7 +28,7 @@ def test_invalid():
def test_access():
with pytest.raises(AttributeError) as e_info:
gnd = dpsim.dp.Node.GND()
c = dpsim.dp.ph1.Capacitor('c1', [gnd, gnd], capacitance=1.234);
c = dpsim.dp.ph1.Capacitor('c1', [gnd, gnd], C=1.234);
# Current is a read-only property.
# This should throw a AttributeError exception!
......@@ -37,8 +37,8 @@ def test_access():
def test_type():
with pytest.raises(TypeError) as e_info:
gnd = dpsim.dp.Node.GND()
c = dpsim.dp.ph1.Capacitor('c1', [gnd, gnd], capacitance=1.234);
c = dpsim.dp.ph1.Capacitor('c1', [gnd, gnd], C=1.234);
# Capacitance is a real valued property.
# Assigning a complex number should throw a TypeError exception!
c.capacitance = 1j
c.C = 1j
......@@ -3,18 +3,18 @@ import dpsim
PATH = os.path.dirname(__file__)
def no_test_circuit():
def test_circuit():
# Nodes
gnd = dpsim.dp.Node.GND()
n1 = dpsim.dp.Node("n1")
n2 = dpsim.dp.Node("n2")
n3 = dpsim.dp.Node("n3")
n1 = dpsim.dp.Node('n1')
n2 = dpsim.dp.Node('n2')
n3 = dpsim.dp.Node('n3')
# Components
v1 = dpsim.dp.ph1.VoltageSource("v_1", [gnd, n1], v_ref=10)
lL = dpsim.dp.ph1.Inductor("l_L", [n2, n3], inductance=0.001)
rL = dpsim.dp.ph1.Resistor("r_L", [n1, n2], resistance=0.1)
r1 = dpsim.dp.ph1.Resistor("r_1", [n3, gnd], resistance=20)
v1 = dpsim.dp.ph1.VoltageSource('v_1', [gnd, n1], V_ref=10)
lL = dpsim.dp.ph1.Inductor('l_L', [n2, n3], L=0.001)
rL = dpsim.dp.ph1.Resistor('r_L', [n1, n2], R=0.1)
r1 = dpsim.dp.ph1.Resistor('r_1', [n3, gnd], R=20)
system = dpsim.SystemTopology(50, [gnd, n1, n2, n3], [v1, lL, rL, r1])
......@@ -28,9 +28,9 @@ def no_test_circuit():
#err += ts.TimeSeries.rmse(expected[0], results[0].dynphasor_shift_to_emt('n1_emt', 50))
#err += ts.TimeSeries.rmse(expected[1], results[1].dynphasor_shift_to_emt('n2_emt', 50))
print("Total RMSE: %g" % (err))
print('Total RMSE: %g' % (err))
assert err < 1e-4
if __name__ == "__main__":
if __name__ == '__main__':
test_circuit()
......@@ -3,14 +3,14 @@ import datetime as dt
from dpsim.Event import Event
def no_test_realtime():
def test_realtime():
# Nodes
gnd = dpsim.dp.Node.GND()
n1 = dpsim.dp.Node("n1")
n1 = dpsim.dp.Node('n1')
# Components
v1 = dpsim.dp.ph1.VoltageSource("v_1", [gnd, n1], v_ref=10)
r1 = dpsim.dp.ph1.Resistor("r_1", [n1, gnd], resistance=1)
v1 = dpsim.dp.ph1.VoltageSource('v_1', [gnd, n1], V_ref=10)
r1 = dpsim.dp.ph1.Resistor('r_1', [n1, gnd], R=1)
system = dpsim.SystemTopology(50, [gnd, n1], [v1, r1])
......@@ -23,5 +23,5 @@ def no_test_realtime():
sim.run(pbar=True)
if __name__ == "__main__":
if __name__ == '__main__':
test_realtime()
......@@ -4,13 +4,13 @@ import logging
from dpsim.Event import Event
def no_test_simulation():
def test_simulation():
logging.getLogger().setLevel(logging.DEBUG)
logging.info("hello\n")
logging.info('hello\n')
n1 = dpsim.dp.Node("n1")
n1 = dpsim.dp.Node('n1')
gnd = dpsim.dp.Node.GND()
r = dpsim.dp.ph1.Resistor("r1", [gnd, n1])
r = dpsim.dp.ph1.Resistor('r1', [gnd, n1])
sys = dpsim.SystemTopology(50, [n1], [r])
......@@ -48,5 +48,5 @@ def no_test_simulation():
assert sim.wait_until() == Event.stopping
assert sim.wait_until() == Event.stopped
if __name__ == "__main__":
if __name__ == '__main__':
test_simulation()
......@@ -4,14 +4,14 @@ import logging
from dpsim.Event import Event
def no_test_simulation():
def test_simulation():
logging.getLogger().setLevel(logging.DEBUG)
logging.info("hello\n")
logging.info('hello\n')
n1 = dpsim.dp.Node("n1")
n1 = dpsim.dp.Node('n1')
gnd = dpsim.dp.Node.GND()
r = dpsim.dp.ph1.Resistor("r1", [gnd, n1])
r = dpsim.dp.ph1.Resistor('r1', [gnd, n1])
sys = dpsim.SystemTopology(50, [n1], [r])
......@@ -34,5 +34,5 @@ def no_test_simulation():
assert sim.wait_until() == Event.stopped
if __name__ == "__main__":
if __name__ == '__main__':
test_simulation()
......@@ -38,8 +38,6 @@ namespace DPsim {
std::ofstream mLogFile;
Bool mEnabled;
static std::ostringstream mNullStream;
static std::ostream& nullStream();
std::map<String, CPS::AttributeBase::Ptr> mAttributes;
......
......@@ -76,6 +76,7 @@ namespace Python {
double realTimeStep; /// effective timestep for real-time simulation
bool realTime;
bool startSync;
bool failOnOverrun;
bool singleStepping; /// Debugger like stepping for simulations
Timer::StartTimePoint startTime;
......
......@@ -39,7 +39,7 @@ namespace Python {
struct SystemTopology {
PyObject_HEAD
std::shared_ptr<CPS::SystemTopology> sys;
CPS::SystemTopology::Ptr sys;
PyObject *pyNodeDict;
PyObject *pyComponentDict;
......
This diff is collapsed.
......@@ -27,8 +27,6 @@ namespace fs = std::experimental::filesystem;
using namespace DPsim;
std::ostringstream DataLogger::mNullStream;
DataLogger::DataLogger(Bool enabled) :
mLogFile(),
mEnabled(enabled) {
......@@ -130,14 +128,6 @@ void DataLogger::logEMTNodeValues(Real time, const Matrix& data) {
logDataLine(time, data);
}
std::ostream& DataLogger::nullStream() {
if (mNullStream.good()) {
mNullStream.setstate(std::ios_base::badbit);
}
return mNullStream;
}
void DataLogger::log(Real time) {
if (mLogFile.tellp() == std::ofstream::pos_type(0)) {
mLogFile << std::right << std::setw(14) << "time";
......
......@@ -81,8 +81,10 @@ void Python::Simulation::threadFunction(Python::Simulation *self)
catch (Timer::OverrunException e) {
std::unique_lock<std::mutex> lk(*self->mut);
newState(self, Simulation::State::overrun);
self->cond->notify_one();
if (self->failOnOverrun) {
newState(self, Simulation::State::overrun);
self->cond->notify_one();
}
}
}
......@@ -151,10 +153,11 @@ PyObject* Python::Simulation::newfunc(PyTypeObject* subtype, PyObject *args, PyO
int Python::Simulation::init(Simulation* self, PyObject *args, PyObject *kwds)
{
static const char *kwlist[] = {"name", "system", "timestep", "duration", "start_time", "start_time_us", "sim_type", "solver_type", "single_stepping", "rt", "rt_factor", "start_sync", "init_steady_state", "log_level", nullptr};
static const char *kwlist[] = {"name", "system", "timestep", "duration", "start_time", "start_time_us", "sim_type", "solver_type", "single_stepping", "rt", "rt_factor", "start_sync", "init_steady_state", "log_level", "fail_on_overrun", nullptr};
double timestep = 1e-3, duration = DBL_MAX, rtFactor = 1;
const char *name = nullptr;
int t = 0, s = 0, rt = 0, ss = 0, st = 0, initSteadyState = 0;
int failOnOverrun = 0;
CPS::Logger::Level logLevel = CPS::Logger::Level::INFO;
......@@ -164,8 +167,8 @@ int Python::Simulation::init(Simulation* self, PyObject *args, PyObject *kwds)
enum Solver::Type solverType;
enum Domain domain;
if (!PyArg_ParseTupleAndKeywords(args, kwds, "sO|ddkkiippdppi", (char **) kwlist,
&name, &self->pySys, &timestep, &duration, &startTime, &startTimeUs, &s, &t, &ss, &rt, &rtFactor, &st, &initSteadyState, &logLevel)) {
if (!PyArg_ParseTupleAndKeywords(args, kwds, "sO|ddkkiippdppip", (char **) kwlist,
&name, &self->pySys, &timestep, &duration, &startTime, &startTimeUs, &s, &t, &ss, &rt, &rtFactor, &st, &initSteadyState, &logLevel, &failOnOverrun)) {
return -1;
}
......@@ -173,6 +176,7 @@ int Python::Simulation::init(Simulation* self, PyObject *args, PyObject *kwds)
self->realTime = rt;
self->startSync = ss;
self->singleStepping = st;
self->failOnOverrun = failOnOverrun;
self->realTimeStep = timestep / rtFactor;
if (startTime > 0) {
......
......@@ -80,7 +80,7 @@ class Simulation(_dpsim.Simulation):
LOGGER.info('Finished simulation!')
def overrun(self, *args):
LOGGER.warn('Overrun in simulation!');
raise RuntimeError("Simulation overrun!")
async def __update_progressbar_task(self):
while self.time < self.final_time:
......
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