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Power System Simulation and Optimization
DPsim
DPsim
Commits
a8434448
Commit
a8434448
authored
Dec 17, 2019
by
Jan Dinkelbach
Committed by
Markus Mirz
Jan 31, 2020
Browse files
pfsolver: allow vd and pv comps at same bus using vd as default
parent
7c60d93b
Changes
1
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Source/PFSolver.cpp
View file @
a8434448
...
...
@@ -164,10 +164,16 @@ void PFSolver::determinePFBusType() {
else
if
(
connectedPV
&&
connectedPQ
&&
!
connectedVD
)
{
mPVBusIndices
.
push_back
(
node
->
simNode
());
mPVBuses
.
push_back
(
node
);
mSLog
->
info
(
"Note: node with uuid {} set as PV bus. Both PV and PQ type components were connected."
,
node
->
attribute
<
String
>
(
"uid"
)
->
get
());
}
// only VD type component connected -> set as VD bus
else
if
(
!
connectedPV
&&
!
connectedPQ
&&
connectedVD
)
{
mVDBusIndices
.
push_back
(
node
->
simNode
());
mVDBuses
.
push_back
(
node
);
}
// VD and PV type component connect -> set as VD bus
else
if
(
connectedPV
&&
!
connectedPQ
&&
connectedVD
)
{
mVDBusIndices
.
push_back
(
node
->
simNode
());
mVDBuses
.
push_back
(
node
);
mSLog
->
info
(
"Note: node with uuid {} set as VD bus. Both VD and PV type components were connected."
,
node
->
attribute
<
String
>
(
"uid"
)
->
get
());
}
else
{
std
::
stringstream
ss
;
...
...
Jan Dinkelbach
@jan.dinkelbach
mentioned in commit
65a000be
·
Feb 13, 2020
mentioned in commit
65a000be
mentioned in commit 65a000be7267d0518688e10c50b7d0b1681a7509
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