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Power System Simulation and Optimization
DPsim
DPsim
Commits
5b1fd123
Commit
5b1fd123
authored
Sep 25, 2018
by
Markus Mirz
Browse files
update cmake for examples
parent
dedebdfb
Changes
1
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Inline
Side-by-side
Examples/Cxx/CMakeLists.txt
View file @
5b1fd123
...
...
@@ -8,25 +8,29 @@ endif()
# targets
set
(
CIRCUIT_SOURCES
Circuits/DP_IdealVS_R_1.cpp
Circuits/DP_CS_R_1.cpp
Circuits/DP_IdealVS_RL1.cpp
Circuits/DP_IdealVS_RC1.cpp
# Dynamic phasor examples
Circuits/DP_VS_R1.cpp
Circuits/DP_CS_R1.cpp
Circuits/DP_VS_RL1.cpp
Circuits/DP_VS_RC1.cpp
Circuits/DP_CS_R2CL.cpp
Circuits/DP_IdealVS_CS_R4_1a.cpp
Circuits/DP_IdealVS_CS_R4_1b.cpp
Circuits/DP_IdealVS_R2L3.cpp
Circuits/EMT_CS_R_1.cpp
Circuits/EMT_IdealVS_RL1.cpp
Circuits/DP_VS_CS_R4.cpp
Circuits/DP_VS_R2L3.cpp
#Circuits/DP_VS_PiLine_R.cpp
#Circuits/DP_VS_Trafo_R.cpp
#Circuits/DP_ResVS_RL_Switch.cpp
# EMT examples
Circuits/EMT_VS_R1.cpp
Circuits/EMT_CS_R1.cpp
Circuits/EMT_VS_RL1.cpp
Circuits/EMT_CS_R2CL.cpp
Circuits/EMT_IdealVS_R2L3.cpp
Circuits/EMT_IdealVS_CS_R4_1a.cpp
Circuits/EMT_IdealVS_CS_R4_1b.cpp
#Circuits/DP_IdealVS_RXLine_1.cpp
#Circuits/DP_IdealVS_Trafo_1.cpp
#Circuits/DP_ResVS_RL_Switch_1.cpp
#Circuits/EMT_IdealVS_R_1.cpp
#Circuits/EMT_ResVS_RL_Switch_1.cpp
Circuits/EMT_VS_R2L3.cpp
Circuits/EMT_VS_CS_R4_AC.cpp
Circuits/EMT_VS_CS_R4_DC.cpp
#Circuits/EMT_ResVS_RL_Switch.cpp
)
set
(
SYNCGEN_SOURCES
...
...
@@ -60,10 +64,12 @@ if(WITH_SUNDIALS)
)
endif
()
set
(
RT_SOURCES
if
(
WITH_RT
)
set
(
RT_SOURCES
RealTime/RT_DP_CS_R_1.cpp
RealTime/RT_DP_ResVS_RL1.cpp
)
)
endif
()
if
(
WITH_SHMEM
)
list
(
APPEND LIBRARIES
${
VILLASNODE_LIBRARIES
}
)
...
...
@@ -84,8 +90,14 @@ if(WITH_CIM)
list
(
APPEND LIBRARIES
${
CIMPP_LIBRARIES
}
)
list
(
APPEND INCLUDE_DIRS
${
CIMPP_INCLUDE_DIRS
}
)
set
(
CIM_SOURCES
if
(
NOT WIN32
)
set
(
CIM_SOURCES_POSIX
CIM/dpsim-cim.cpp
)
endif
()
set
(
CIM_SOURCES
CIM/WSCC-9bus_CIM.cpp
CIM/WSCC-9bus_CIM_Dyn.cpp
CIM/WSCC-9bus_CIM_Dyn_Switch.cpp
...
...
@@ -105,7 +117,7 @@ if(WITH_PYTHON)
list
(
APPEND INCLUDE_DIRS
${
PYTHON_INCLUDE_DIRS
}
)
endif
()
foreach
(
SOURCE
${
CIRCUIT_SOURCES
}
${
SYNCGEN_SOURCES
}
${
VARFREQ_SOURCES
}
${
SHMEM_SOURCES
}
${
RT_SOURCES
}
${
CIM_SOURCES
}
${
CIM_SHMEM_SOURCES
}
${
DAE_SOURCES
}
)
foreach
(
SOURCE
${
CIRCUIT_SOURCES
}
${
SYNCGEN_SOURCES
}
${
VARFREQ_SOURCES
}
${
SHMEM_SOURCES
}
${
RT_SOURCES
}
${
CIM_SOURCES
}
${
CIM_SOURCES_POSIX
}
${
CIM_SHMEM_SOURCES
}
${
DAE_SOURCES
}
)
get_filename_component
(
TARGET
${
SOURCE
}
NAME_WE
)
add_executable
(
${
TARGET
}
${
SOURCE
}
)
...
...
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