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Public
Power System Simulation and Optimization
DPsim
DPsim
Commits
189c69b2
Commit
189c69b2
authored
Sep 17, 2018
by
Markus Mirz
Browse files
fix example
Former-commit-id:
61422669
parent
1cd7e49a
Changes
1
Hide whitespace changes
Inline
Side-by-side
Examples/Cxx/Circuits/DP_IdealVS_RL1.cpp
View file @
189c69b2
...
...
@@ -32,9 +32,13 @@ int main(int argc, char* argv[]) {
// Components
auto
vs
=
VoltageSource
::
make
(
"vs"
);
vs
->
setParameters
(
Complex
(
10
,
0
));
vs
->
connect
(
Node
::
List
{
Node
::
GND
,
n1
});
auto
r1
=
Resistor
::
make
(
"r_1"
);
r1
->
setParameters
(
5
);
r1
->
connect
(
Node
::
List
{
n1
,
n2
});
auto
l1
=
Inductor
::
make
(
"l_1"
);
l1
->
setParameters
(
0.02
);
l1
->
connect
(
Node
::
List
{
n2
,
Node
::
GND
});
...
...
@@ -47,7 +51,15 @@ int main(int argc, char* argv[]) {
Real
finalTime
=
0.1
;
String
simName
=
"DP_IdealVS_RL1"
;
// Logger
auto
logger
=
DataLogger
::
make
(
simName
);
logger
->
addAttribute
(
"v1"
,
n1
->
attribute
(
"voltage"
));
logger
->
addAttribute
(
"v2"
,
n2
->
attribute
(
"voltage"
));
logger
->
addAttribute
(
"i1"
,
r1
->
attribute
(
"i_comp"
));
Simulation
sim
(
simName
,
sys
,
timeStep
,
finalTime
);
sim
.
addLogger
(
logger
);
sim
.
run
();
return
0
;
...
...
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