This project is mirrored from https://github.com/hermitcore/libhermit-rs.git. Pull mirroring updated .
  1. 17 Aug, 2021 5 commits
  2. 17 Jun, 2021 1 commit
  3. 29 May, 2021 1 commit
  4. 16 Dec, 2020 1 commit
  5. 15 Dec, 2020 1 commit
  6. 11 Sep, 2020 1 commit
  7. 31 Aug, 2020 2 commits
  8. 26 Jun, 2020 1 commit
  9. 01 Jun, 2020 1 commit
    • jschwe's avatar
      Add UTF-8 support to Console (#69) · 63e1f5ba
      jschwe authored
      - Swap order of write_char and write_str to match order of trait
      - Implement write_char by calling write_str to match the implementation in the standard library
      - Add output_message_buf for printing of a buffer.
      - Convert str to UTF-8 encoded byte buffer before printing.
      63e1f5ba
  10. 21 May, 2020 1 commit
    • jschwe's avatar
      Refactor libhermit-rs for rust edition 2018 (#59) · d793a9b1
      jschwe authored
      * Refactor: Fix Clippy warnings
      
      - Added support for empty println!()
      - use short hand initialization when possible
      - replace if x==false with if !x
      - replace unwrap_or(function_call()) with unwrap_or_else(|| function_call())
      - and others
      
      * Update to Rust edition 2018
       - Mostly just adds crate::
      d793a9b1
  11. 13 Aug, 2019 1 commit
  12. 06 Jul, 2019 1 commit
  13. 16 Jun, 2019 2 commits
  14. 10 Jun, 2019 1 commit
  15. 18 Jan, 2019 1 commit
  16. 05 Jan, 2019 1 commit
  17. 02 Jan, 2019 1 commit
  18. 24 Jul, 2018 1 commit
    • Colin Finck's avatar
      The first real AArch64 bringup commit for HermitCore-rs · a9671ff5
      Colin Finck authored
      * Split the CMake files into an architecture-independent and an architecture-dependent part.
        This overhaul of the build system also removes the custom "module system", which doesn't make much sense for a Rust kernel and doesn't work well with such a split configuration.
      * Add an aarch64-unknown-hermit-kernel.json target for Xargo.
      * Implement basic IRQ and serial port functions for AArch64 to get a first output.
      * Copy the 4-level paging from x86_64 to AArch64 and remove the parts relying on the "x86" crate.
        While this still needs some work to get the names and flags right, 4-level paging should generally work on AArch64 with the same concepts that are used for x86_64.
      * Comment out and stub out many functions for AArch64 to let is somewhat compile.
      * Redefine core_id as a CPU number that is guaranteed to be sequential to make it architecture-independent.
        For x86_64, this number is now translated to a Local APIC ID in the "apic" module only.
      * Add a per-architecture TaskStacks structure, which contains "stack" and "ist" on x86_64 and only "stack" on AArch64.
      * Add a per-architecture network_adapter_init function to initialize RTL8139 only for x86_64.
      * Get rid of the top-level "arch" directory and put the reasonable architecture-dependent include files into /include/hermit/<ARCH>, all prefixed with "arch_".
      * Make the inclusion of some crates dependent on the target architecture.
      * Rename get_number_of_processors to get_processor_count and make it return a usize.
      a9671ff5
  19. 08 Nov, 2017 1 commit
    • Colin Finck's avatar
      Make HermitCore's entry point a Rust function, fully implement Paging in Rust... · 77d69db1
      Colin Finck authored
      Make HermitCore's entry point a Rust function, fully implement Paging in Rust along with most of the CPU Initialization.
      
      * Initializing the OS in Rust enables us to keep many functions internal (like GDT and IDT installation) without exporting them to the C world.
      * Use __core_id.per_core() instead of the dummy core_id! macro in set_tss.
        Fixes multithreaded applications, which were broken since set_tss has been converted to Rust code.
      * Reimplement processor.rs based on raw_cpuid.
        Only take over the checks from processor.c, which make sense on x86-64. FPU, FXSR, MCE, NX, SSE2 are guaranteed to be available.
      * Add more assertions to the Paging code. They also take CPU capabilities into account now (Physical Address Width and 1GiB Page Support).
      
      This is still a big Work-In-Progress!
      More documentation and higher sophisticated APIs/structures are going to follow later.
      77d69db1
  20. 30 Oct, 2017 2 commits
  21. 21 Oct, 2017 1 commit
  22. 06 Aug, 2017 1 commit
  23. 22 Jul, 2017 1 commit
  24. 20 Jul, 2017 1 commit