This project is mirrored from https://github.com/hermitcore/libhermit-rs.git. Pull mirroring updated .
  1. 04 Jan, 2018 2 commits
  2. 03 Jan, 2018 1 commit
    • Colin Finck's avatar
      Rewrite the HermitCore Loader in Rust and reorganize the CMake Buildsystem. · 663f84c9
      Colin Finck authored
      We now only build the Rust components and their dependencies.
      Every Rust component also has its own CMakeLists.txt file now.
      Therefore, the HermitCore C version can be removed in the next step.
      
      The Loader reuses the Macros, Paging, and Serial Port implementation of the HermitCore Kernel.
      It builds, but is still untested.
      663f84c9
  3. 21 Dec, 2017 1 commit
    • Colin Finck's avatar
      Port over the lwIP-based network stack along with an Intel E1000 driver from... · 7542f2f7
      Colin Finck authored
      Port over the lwIP-based network stack along with an Intel E1000 driver from the HermitCore C version.
      
      I have built some Rust helper functions around lwIP to make it more comfortable and split up the lwIP network interface from the E1000 network adapter.
      However, using the lwIP C library requires many unsafe blocks and usage of raw pointers.
      
      This is still untested and requires the scheduler implementation first.
      7542f2f7
  4. 20 Dec, 2017 5 commits
  5. 13 Dec, 2017 4 commits
  6. 11 Dec, 2017 5 commits
  7. 08 Dec, 2017 1 commit
    • Colin Finck's avatar
      Commit 5e3ed9f76535a498e8ef37d8e1040c2311daa7f9 for the DoublyLinkedList implemented in Safe Rust. · 7eaab769
      Colin Finck authored
      Note that the unsafe implementation uses pointers and could call internal_allocate to allocate a new
      node without locking. On the other hand, the safe implementation uses Rc, which always calls into our
      allocator the same way.
      
      Therefore, the global MM_LOCK was replaced by a custom MmLock that checks if a call originates from the same
      CPU core. In that case, no further locking is done. This prevents deadlocks when doing recursive calls
      from the Memory Manager into other Memory Manager functions.
      
      Recursive calls also need to be handled in the NodePool.
      When a maintenance is already in progress, a recursive call into maintain() must exit immediately.
      
      With these changes, we now have a stable Memory Manager implemented in two versions:
      Safe with Rust allocations and borrow-checking as well as unsafe with traditional pointers.
      They can now be compared in a further step.
      7eaab769
  8. 07 Dec, 2017 1 commit
  9. 02 Dec, 2017 1 commit
    • Colin Finck's avatar
      Fix APIC Interrupts such as the TLB Flush IPI. · 007dc5ab
      Colin Finck authored
      * Don't write more than 32 bits into the 32-bit xAPIC registers. Fixes APIC initialization.
      * xAPIC also requires to check the "Delivery Status" bit after writing to ICR1. Do that.
      * Add missing APIC_ICR_LEVEL_ASSERT in ipi_tlb_flush.
      007dc5ab
  10. 29 Nov, 2017 1 commit
    • Colin Finck's avatar
      Fix Deadlocks and Free List corruptions in Memory Management. · d7eec95b
      Colin Finck authored
      * Put locking into the FreeList implementation instead of its users.
        Release the lock every time we are allocating or freeing memory.
        As Free Lists are used to manage both physical and virtual memory, not releasing the lock would lead to deadlocks.
      
      * Remove unmapping of pages. It doesn't give us any benefits, because you can always remap an existing entry.
        By removing this feature, we can now guarantee that existing page tables are never freed.
        This allows us to reduce locking from a global paging lock to a short lock when entries are read or written.
      
      * Check that more than one CPU is available (and thus that APIC has been initialized) before attempting to send a TLB Flush IPI.
      
      The new code now successfully boots up in QEMU with 64 CPUs in SMP :)
      d7eec95b
  11. 27 Nov, 2017 1 commit
    • Colin Finck's avatar
      Improve Debugging, Logging, and fix many bugs and warnings in the process: · 10b9dcc3
      Colin Finck authored
      * APIC structures need packing.
      * The MultiProcessor Floating Pointer structure needs to be looked up in 4 byte steps, not 4 KiB steps.
      * Even though it contains redundant information, we cannot skip the 82489DX-style INIT IPI for initializing an application processor.
        The startup procedure for application processors now fully conforms to the Intel MultiProcessor Specification 1.4.
      * xAPIC's ICR1 and ICR2 registers have a gap between them. Therefore, we need to write to them separately.
      * Add "volatile" to all asm! macros and read external global variables altered by other CPUs through ptr::read_volatile.
      * Early x86-64 CPUs don't return CPUID Extended Feature Info. Don't depend on that.
      * Restore parts of the Page Fault Handler to return an error message.
      * Simplify debugging macros and report the Core ID with every message.
      * Initialize the Core ID earlier at boot and make it available through the core_id() inline function.
      * Fix Timer interrupt function declaration.
      * Fix deallocation from a Free List. There are more possible cases and no way it can fail.
      
      The Rust version of HermitCore now boots up with up to 4 CPUs.
      More CPUs currently trigger a bug in memory management.
      10b9dcc3
  12. 24 Nov, 2017 2 commits
  13. 23 Nov, 2017 1 commit
    • Colin Finck's avatar
      Implement parsing MultiProcessor tables, initializing APIC, initializing SMP,... · 77bd5d1d
      Colin Finck authored
      Implement parsing MultiProcessor tables, initializing APIC, initializing SMP, and port over the interrupt handling in Rust from eduOS-rs.
      
      MAX_CORES is reduced to 256, because MultiProcessor tables don't support more than that.
      entry.asm is relicensed to MIT just like the rest of the eduOS-rs and HermitCore Rust code.
      Also improve debugging and make use of the or_else/unwrap_or_else Rust functions.
      
      This is all untested work in progress! At least it compiles :)
      77bd5d1d
  14. 20 Nov, 2017 1 commit
    • Colin Finck's avatar
      Implement physical and virtual memory managers, a FreeList for both, an even... · ee46872e
      Colin Finck authored
      Implement physical and virtual memory managers, a FreeList for both, an even more generic DoublyLinkedList in Safe Rust, and a custom allocator.
      
      The data structures used to manage heap memory require dynamic memory allocations themselves.
      To solve this chicken-egg problem, I have introduced a "Bootstrap Allocator". This is a simple
      single-threaded implementation of a bump allocator using some preallocated space.
      As soon as all required data structures have been set up, the more sophisticated "System Allocator"
      is used.
      
      This code finally breaks compatibility with the HermitCore C implementation.
      It compiles, but applications can only be run again when the remaining kernel components have been ported.
      ee46872e
  15. 14 Nov, 2017 2 commits
  16. 13 Nov, 2017 1 commit
    • Colin Finck's avatar
      Port over Dynamic Ticks, IRQ handling, PIC, PIT, and SpeedStep functions to... · a3c8174f
      Colin Finck authored
      Port over Dynamic Ticks, IRQ handling, PIC, PIT, and SpeedStep functions to Rust and improve the GDT code.
      
      Functions accessing the PIC are now properly separated from the rest of the IRQ handling to allow for a clean APIC implementation later.
      Also the PIT is separated from the Timer functions, because it is only meant to be used for measuring the CPU frequency.
      
      The GDT code allocates all 4 ISTs per core now and sets the TSS, so that interrupts can be enabled sooner.
      This also means that IST1 is no longer allocated per task, but a single IST1 is shared among all tasks on a core.
      
      Furthermore, some more Rust features have been introduced: Question mark and "if let" statements.
      
      This change breaks using HermitCore applications until the APIC, Memory, Task, and IRQ Handlers have been ported.
      a3c8174f
  17. 11 Nov, 2017 1 commit
  18. 09 Nov, 2017 1 commit
  19. 08 Nov, 2017 3 commits
    • Colin Finck's avatar
      b4808110
    • Colin Finck's avatar
      Make HermitCore's entry point a Rust function, fully implement Paging in Rust... · 77d69db1
      Colin Finck authored
      Make HermitCore's entry point a Rust function, fully implement Paging in Rust along with most of the CPU Initialization.
      
      * Initializing the OS in Rust enables us to keep many functions internal (like GDT and IDT installation) without exporting them to the C world.
      * Use __core_id.per_core() instead of the dummy core_id! macro in set_tss.
        Fixes multithreaded applications, which were broken since set_tss has been converted to Rust code.
      * Reimplement processor.rs based on raw_cpuid.
        Only take over the checks from processor.c, which make sense on x86-64. FPU, FXSR, MCE, NX, SSE2 are guaranteed to be available.
      * Add more assertions to the Paging code. They also take CPU capabilities into account now (Physical Address Width and 1GiB Page Support).
      
      This is still a big Work-In-Progress!
      More documentation and higher sophisticated APIs/structures are going to follow later.
      77d69db1
    • Colin Finck's avatar
      Implement per_core and set_per_core as trait functions for every 4-byte and 8-byte variable type. · 2821998c
      Colin Finck authored
      This also deprecates the dummy core_id! macro by a proper call to __core_id.per_core()
      2821998c
  20. 30 Oct, 2017 5 commits