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  1. 21 Sep, 2020 1 commit
  2. 20 Sep, 2020 3 commits
  3. 07 Sep, 2020 1 commit
    • Stefan Lankes's avatar
      add dependency to `Send` for the implementation of spinlock (#97) · 74d79d77
      Stefan Lankes authored
      * add requirement to use only types T for spin lock, where the behavior Send is specified
      * remove obsolete implementation of a irqsave refcell
      * replace DoubleLinkedList by LinkedList of the alloc library
      * using of the core collection library to handle memory and tasks
      * the vector of PCI adapters aren't longer protected by a lock because these adapter are initialized at boot time. Afterwards, we have only read-access.
      * Freelist: add check if a reunion with the previous slot is possible
  4. 10 Aug, 2020 1 commit
  5. 31 May, 2020 1 commit
  6. 21 May, 2020 1 commit
    • jschwe's avatar
      Refactor libhermit-rs for rust edition 2018 (#59) · d793a9b1
      jschwe authored
      * Refactor: Fix Clippy warnings
      - Added support for empty println!()
      - use short hand initialization when possible
      - replace if x==false with if !x
      - replace unwrap_or(function_call()) with unwrap_or_else(|| function_call())
      - and others
      * Update to Rust edition 2018
       - Mostly just adds crate::
  7. 25 Apr, 2020 1 commit
    • Stefan Lankes's avatar
      separate kernel and user space stack · 41cf625c
      Stefan Lankes authored
      - introduce macros to switch between kernel and user space
      - add core-specific variable to store the address of the kernel stack
      - add task value to store the latest user-space stack pointer
  8. 17 Apr, 2020 1 commit
  9. 16 Apr, 2020 1 commit
  10. 15 Apr, 2020 2 commits
  11. 14 Apr, 2020 2 commits
  12. 11 Apr, 2020 1 commit
  13. 08 Apr, 2020 1 commit
  14. 08 Mar, 2020 1 commit
  15. 23 Feb, 2020 1 commit
  16. 03 Feb, 2020 1 commit
  17. 17 Aug, 2019 1 commit
  18. 13 Aug, 2019 1 commit
  19. 03 Aug, 2019 1 commit
  20. 16 Jul, 2019 1 commit
  21. 15 Jul, 2019 1 commit
  22. 13 Jul, 2019 2 commits
  23. 07 Jul, 2019 1 commit
  24. 06 Jul, 2019 1 commit
  25. 25 Jun, 2019 1 commit
  26. 16 Jun, 2019 2 commits
  27. 10 Jun, 2019 1 commit
  28. 02 Jun, 2019 1 commit
  29. 04 May, 2019 2 commits
  30. 16 Jan, 2019 1 commit
  31. 26 Jul, 2018 1 commit
    • Colin Finck's avatar
      Port the Memory Manager to AArch64, with full support for 4-level Paging, 4... · a711534f
      Colin Finck authored
      Port the Memory Manager to AArch64, with full support for 4-level Paging, 4 KiB, 2 MiB, and 1 GiB Pages, and Execute-Disable!
      * Make PageTableEntryFlags architecture-independent by adding builder pattern methods.
        Instead of providing PageTableEntryFlags::EXECUTE_DISABLE, one simply uses the execute_disable() method now.
        The different implementations of each method for AArch64 and x86_64 map to the respective architecture flags.
      * Make a boolean execute_disable the only additional parameter for mm::allocate() to make it architecture-independent.
      * Remove the do_ipi parameter from paging functions.
        It was x86_64-specific and there is nothing wrong with always doing an IPI when necessary and application processors have been booted.
      * Make the LEVEL/MAP_LEVEL constant ascending instead of descending for the AArch64 implementation to match with the Page Table names (L0, L1, etc.).
  32. 24 Jul, 2018 1 commit
    • Colin Finck's avatar
      The first real AArch64 bringup commit for HermitCore-rs · a9671ff5
      Colin Finck authored
      * Split the CMake files into an architecture-independent and an architecture-dependent part.
        This overhaul of the build system also removes the custom "module system", which doesn't make much sense for a Rust kernel and doesn't work well with such a split configuration.
      * Add an aarch64-unknown-hermit-kernel.json target for Xargo.
      * Implement basic IRQ and serial port functions for AArch64 to get a first output.
      * Copy the 4-level paging from x86_64 to AArch64 and remove the parts relying on the "x86" crate.
        While this still needs some work to get the names and flags right, 4-level paging should generally work on AArch64 with the same concepts that are used for x86_64.
      * Comment out and stub out many functions for AArch64 to let is somewhat compile.
      * Redefine core_id as a CPU number that is guaranteed to be sequential to make it architecture-independent.
        For x86_64, this number is now translated to a Local APIC ID in the "apic" module only.
      * Add a per-architecture TaskStacks structure, which contains "stack" and "ist" on x86_64 and only "stack" on AArch64.
      * Add a per-architecture network_adapter_init function to initialize RTL8139 only for x86_64.
      * Get rid of the top-level "arch" directory and put the reasonable architecture-dependent include files into /include/hermit/<ARCH>, all prefixed with "arch_".
      * Make the inclusion of some crates dependent on the target architecture.
      * Rename get_number_of_processors to get_processor_count and make it return a usize.
  33. 29 Jun, 2018 1 commit
    • Colin Finck's avatar
      Overhaul the timing framework to improve the global timer resolution to 1... · aee76165
      Colin Finck authored
      Overhaul the timing framework to improve the global timer resolution to 1 microsecond and simplify the code, also for a later AArch64 port.
      * Rename the udelay() syscall to sys_usleep() for consistence and accept a u64 parameter.
        udelay() with an u32 parameter is still provided to serve the existing customers, but should eventually vanish.
      * Use time values in 1 microsecond granularity and u64 everywhere instead of simulating a 10ms timer with the CPU Time-Stamp Counter.
        This guarantees maximum precision for the best timing function we currently provide (sys_usleep).
        It also simplifies the code, because we can simply add microseconds to the timer tick count.
      * Rewrite update_timer_ticks() as get_timer_ticks().
        It simply divides get_timestamp() by get_frequency() now to simulate a 1 microsecond timer with the CPU Time-Stamp Counter.
        This requires no per-core variables and is much more accurate.
      * Calibrate the Local APIC Timer for 1 microsecond resolution.
        This reduces the maximum timeout to 34 seconds on a Intel Xeon E5-2650 v3 @ 2.30GHz, but for longer timeouts, the one-shot timer would simply
        fire multiple times.
      * Detect CPU support for the TSC-Deadline Mode of the Local APIC Timer and use it.
        This one is easier to program than the legacy One-Shot Mode, even more accurate, and has no maximum timeout.