Unverified Commit 38a797fe authored by Stefan Lankes's avatar Stefan Lankes
Browse files

using orginal version of CachePadded from crossbeam-utils

parent 19a74b53
......@@ -30,6 +30,22 @@ version = "0.1.10"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "4785bdd1c96b2a846b2bd7cc02e86b6b3dbf14e7e53446c4f54c92a361040822"
[[package]]
name = "cfg-if"
version = "1.0.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"
[[package]]
name = "crossbeam-utils"
version = "0.8.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "02d96d1e189ef58269ebe5b97953da3274d83a93af647c2ddd6f9dab28cedb8d"
dependencies = [
"autocfg",
"cfg-if 1.0.0",
]
[[package]]
name = "float-cmp"
version = "0.8.0"
......@@ -45,7 +61,7 @@ version = "0.4.11"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "4fabed175da42fed1fa0746b0ea71f412aa9d35e76e95e59b192c64b9dc2bf8b"
dependencies = [
"cfg-if",
"cfg-if 0.1.10",
]
[[package]]
......@@ -172,6 +188,7 @@ name = "rusty-hermit"
version = "0.3.43"
dependencies = [
"bitflags",
"crossbeam-utils",
"float-cmp",
"log",
"multiboot",
......
......@@ -62,6 +62,7 @@ bitflags = "1.2"
#cfg-if = "0.1"
#byteorder = { version = "1.0", default-features = false }
num-derive = "0.3"
crossbeam-utils = { version = "0.8", default-features = false }
[dependencies.num]
version = "0.2"
......
......@@ -15,7 +15,7 @@ use crate::arch::x86_64::kernel::IRQ_COUNTERS;
use crate::arch::x86_64::mm::paging::{BasePageSize, PageSize, PageTableEntryFlags};
use crate::arch::x86_64::mm::{paging, virtualmem};
use crate::arch::x86_64::mm::{PhysAddr, VirtAddr};
use crate::collections::{irqsave, CachePadded};
use crate::collections::irqsave;
use crate::config::*;
use crate::environment;
use crate::mm;
......@@ -29,6 +29,7 @@ use arch::x86_64::kernel::{idt, irq, percore::*, processor, BOOT_INFO};
use core::convert::TryInto;
use core::sync::atomic::spin_loop_hint;
use core::{cmp, fmt, mem, ptr, u32};
use crossbeam_utils::CachePadded;
const APIC_ICR2: usize = 0x0310;
......
......@@ -7,11 +7,11 @@
use crate::arch::x86_64::kernel::irq::IrqStatistics;
use crate::arch::x86_64::kernel::BOOT_INFO;
use crate::collections::CachePadded;
use crate::scheduler::{CoreId, PerCoreScheduler};
use crate::x86::bits64::task::TaskStateSegment;
use crate::x86::msr::*;
use core::ptr;
use crossbeam_utils::CachePadded;
pub static mut PERCORE: PerCoreVariables = CachePadded::new(PerCoreInnerVariables::new(0));
......
use core::fmt;
use core::ops::{Deref, DerefMut};
/// Pads and aligns a value to the length of a cache line.
///
/// This version is derived from crossbeam-utils and support "const initialization routine".
/// In concurrent programming, sometimes it is desirable to make sure commonly accessed pieces of
/// data are not placed into the same cache line. Updating an atomic value invalides the whole
/// cache line it belongs to, which makes the next access to the same cache line slower for other
/// CPU cores. Use `CachePadded` to ensure updating one piece of data doesn't invalidate other
/// cached data.
///
/// # Size and alignment
///
/// Cache lines are assumed to be N bytes long, depending on the architecture:
///
/// * On x86-64, N = 128.
/// * On all others, N = 64.
///
/// Note that N is just a reasonable guess and is not guaranteed to match the actual cache line
/// length of the machine the program is running on. On modern Intel architectures, spatial
/// prefetcher is pulling pairs of 64-byte cache lines at a time, so we pessimistically assume that
/// cache lines are 128 bytes long.
///
/// The size of `CachePadded<T>` is the smallest multiple of N bytes large enough to accommodate
/// a value of type `T`.
///
/// The alignment of `CachePadded<T>` is the maximum of N bytes and the alignment of `T`.
///
/// # Examples
///
/// Alignment and padding:
///
/// ```
/// use crossbeam_utils::CachePadded;
///
/// let array = [CachePadded::new(1i8), CachePadded::new(2i8)];
/// let addr1 = &*array[0] as *const i8 as usize;
/// let addr2 = &*array[1] as *const i8 as usize;
///
/// assert!(addr2 - addr1 >= 64);
/// assert_eq!(addr1 % 64, 0);
/// assert_eq!(addr2 % 64, 0);
/// ```
///
/// When building a concurrent queue with a head and a tail index, it is wise to place them in
/// different cache lines so that concurrent threads pushing and popping elements don't invalidate
/// each other's cache lines:
///
/// ```
/// use crossbeam_utils::CachePadded;
/// use std::sync::atomic::AtomicUsize;
///
/// struct Queue<T> {
/// head: CachePadded<AtomicUsize>,
/// tail: CachePadded<AtomicUsize>,
/// buffer: *mut T,
/// }
/// ```
#[derive(Clone, Copy, Default, Hash, PartialEq, Eq)]
// Starting from Intel's Sandy Bridge, spatial prefetcher is now pulling pairs of 64-byte cache
// lines at a time, so we have to align to 128 bytes rather than 64.
//
// Sources:
// - https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf
// - https://github.com/facebook/folly/blob/1b5288e6eea6df074758f877c849b6e73bbb9fbb/folly/lang/Align.h#L107
//
// ARM's big.LITTLE architecture has asymmetric cores and "big" cores have 128 byte cache line size
// Sources:
// - https://www.mono-project.com/news/2016/09/12/arm64-icache/
//
#[cfg_attr(any(target_arch = "x86_64", target_arch = "aarch64"), repr(align(128)))]
#[cfg_attr(
not(any(target_arch = "x86_64", target_arch = "aarch64")),
repr(align(64))
)]
pub struct CachePadded<T> {
value: T,
}
unsafe impl<T: Send> Send for CachePadded<T> {}
unsafe impl<T: Sync> Sync for CachePadded<T> {}
impl<T> CachePadded<T> {
/// Pads and aligns a value to the length of a cache line.
///
/// # Examples
///
/// ```
/// use crossbeam_utils::CachePadded;
///
/// let padded_value = CachePadded::new(1);
/// ```
pub const fn new(t: T) -> CachePadded<T> {
CachePadded::<T> { value: t }
}
/// Returns the inner value.
///
/// # Examples
///
/// ```
/// use crossbeam_utils::CachePadded;
///
/// let padded_value = CachePadded::new(7);
/// let value = padded_value.into_inner();
/// assert_eq!(value, 7);
/// ```
pub fn into_inner(self) -> T {
self.value
}
}
impl<T> Deref for CachePadded<T> {
type Target = T;
fn deref(&self) -> &T {
&self.value
}
}
impl<T> DerefMut for CachePadded<T> {
fn deref_mut(&mut self) -> &mut T {
&mut self.value
}
}
impl<T: fmt::Debug> fmt::Debug for CachePadded<T> {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
f.debug_struct("CachePadded")
.field("value", &self.value)
.finish()
}
}
impl<T> From<T> for CachePadded<T> {
fn from(t: T) -> Self {
CachePadded::new(t)
}
}
......@@ -7,10 +7,6 @@
use crate::arch::irq;
mod cachepadded;
pub use self::cachepadded::*;
/// `irqsave` guarantees that the call of the closure
/// will be not disturbed by an interrupt
#[inline]
......
......@@ -8,8 +8,8 @@
//! Kernel Message Buffer for Multi-Kernel mode.
//! Can be read from the Linux side as no serial port is available.
use crate::collections::CachePadded;
use core::sync::atomic::{AtomicUsize, Ordering};
use crossbeam_utils::CachePadded;
const KMSG_SIZE: usize = 0x1000;
......
......@@ -55,6 +55,7 @@
extern crate alloc;
#[macro_use]
extern crate bitflags;
extern crate crossbeam_utils;
#[macro_use]
extern crate log;
#[cfg(target_arch = "x86_64")]
......
......@@ -6,12 +6,12 @@
// copied, modified, or distributed except according to those terms.
use crate::arch::irq;
use crate::collections::CachePadded;
use core::cell::UnsafeCell;
use core::fmt;
use core::marker::Sync;
use core::ops::{Deref, DerefMut, Drop};
use core::sync::atomic::{spin_loop_hint, AtomicBool, AtomicUsize, Ordering};
use crossbeam_utils::CachePadded;
/// This type provides a lock based on busy waiting to realize mutual exclusion of tasks.
///
......
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